Wilson Snyder 2c156d6655 Tests: Reformat some recent tests to mostly verilog-format standard. No test functional change.		2025-12-20 21:46:43 -05:00
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t	Tests: Reformat some recent tests to mostly verilog-format standard. No test functional change.	2025-12-20 21:46:43 -05:00
.gdbinit	…
.gitignore	…
CMakeLists.txt	…
Makefile	…
Makefile_obj	…
driver.py	Tests: Remove old benchmarksim, should use rtlmeter instead	2025-12-16 21:17:27 -05:00
input.vc	…
input.xsim.vc	…