34 lines
716 B
Systemverilog
34 lines
716 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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class Class_A #(
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parameter int myparam = 32
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);
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endclass
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module tb_top;
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localparam int WIDTH_A = 32;
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localparam int WIDTH_B = 2 * 16;
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Class_A #(32) a;
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Class_A #(WIDTH_A) b;
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Class_A #(WIDTH_B) c;
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initial begin
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#1;
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a = b;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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