28 lines
707 B
Systemverilog
28 lines
707 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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module t (/*AUTOARG*/
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// Outputs
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out_data
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);
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output [11:0] out_data;
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wire [11:0] out_data;
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wire [11:0] a;
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wire [2:0] b;
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assign a = 12'h000 ** { b };
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assign b = 3'b0;
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assign out_data = a;
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endmodule
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