22 lines
433 B
Systemverilog
22 lines
433 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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// verilator lint_off COVERIGN
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covergroup cg();
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option.name = "decl_name";
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endgroup
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cg cov1;
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initial begin
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cov1 = new;
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cov1.option.name = "new_cov1_name";
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$finish;
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end
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endmodule
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