59 lines
1.3 KiB
Systemverilog
59 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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int cyc;
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reg [2:0] value;
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int cnt_tt;
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int cnt_tf;
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int cnt_ft;
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int cnt_ff;
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assert property (@(negedge clk) disable iff (value[1]) value[2]) begin
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assert (value[0]) ++cnt_tt;
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else ++cnt_tf;
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end
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else begin
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assert (value[0]) ++cnt_ft;
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else ++cnt_ff;
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end
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// Test loop
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 10) begin
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assert(cyc == 10); // For debug to compare with other asserts
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value <= 0;
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cnt_tt = 0;
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cnt_tf = 0;
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cnt_ft = 0;
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cnt_ff = 0;
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end
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else if (cyc > 10 && cyc < 90) begin
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value <= cyc[2:0];
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end
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else if (cyc == 99) begin
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`checkd(cnt_tt, 10);
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`checkd(cnt_tf, 10);
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`checkd(cnt_ft, 19);
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`checkd(cnt_ff, 11);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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