verilator/test_regress
Steven Hugg 18b0f6387d
Add XML ccall, constpool, initarray, and if/while begins (#3080)
* EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity
* EmitXml: added signed="true" to signed basicdtypes
2021-07-24 21:06:06 -04:00
..
t Add XML ccall, constpool, initarray, and if/while begins (#3080) 2021-07-24 21:06:06 -04:00
.gdbinit Delay parsing of associative arrays until dtypes known. 2020-06-09 07:13:40 -04:00
.gitignore Ignore some files generated by modelsim (#2669) 2020-12-05 21:55:56 -05:00
CMakeLists.txt Add TRACE_THREADS to CMake (#2934) 2021-05-08 08:18:08 -04:00
Makefile Copyright year update 2021-01-01 10:29:54 -05:00
Makefile_obj Copyright year update 2021-01-01 10:29:54 -05:00
driver.pl Emit implementations into separate files based on required headers. 2021-07-22 18:01:07 +01:00
input.vc Internal coverage improvements 2020-09-18 21:27:36 -04:00
input.xsim.vc Add XSim support to driver.pl, bug1493. 2019-08-29 17:00:49 -04:00