Wilson Snyder 1653b982b9 Verilog format		2026-05-13 21:00:34 -04:00
..
t	Verilog format	2026-05-13 21:00:34 -04:00
.gdbinit	…
.gitignore	…
CMakeLists.txt	Remove multi-threaded FST tracing (#7443)	2026-04-19 16:02:12 +01:00
Makefile	Test: Remove old Makefile rules	2026-04-13 21:09:09 -04:00
Makefile_obj	…
driver.py	Tests: Use top shell w/ xrun (#7556)	2026-05-08 16:03:45 -04:00
input.vc	…
input.xsim.vc	…