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Verilog format

This commit is contained in:
Wilson Snyder 2026-05-13 21:00:34 -04:00
parent 1c3ee7ce4c
commit 1653b982b9
82 changed files with 594 additions and 574 deletions
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2
test_regress/t/t_always_combdly.v
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@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
module t (
input clk
input clk
);
integer cyc;

20
test_regress/t/t_case_inside_call_count.v
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@ -8,12 +8,12 @@ class Cls;
int callCount = 0;
int callCount2 = 0;
int value = 6;
bit[5:0] value2 = 6;
bit [5:0] value2 = 6;
function int get();
callCount += 1;
return value;
endfunction
function bit[5:0] get2();
function bit [5:0] get2();
callCount2 += 1;
return value2;
endfunction
@ -28,25 +28,25 @@ module t;
bit called;
c = new;
case (c.get()) inside
[0:5]: $stop;
[6:6]: called = 1;
[7:100]: $stop;
[0 : 5]: $stop;
[6 : 6]: called = 1;
[7 : 100]: $stop;
default: $stop;
endcase
if (!called) $stop;
if (c.callCount != 1) $stop;
called = 0;
case (c.get2()) inside
[0:5]: $stop;
[6:6]: called = 1;
[7:100]: $stop;
[0 : 5]: $stop;
[6 : 6]: called = 1;
[7 : 100]: $stop;
default: $stop;
endcase
if (!called) $stop;
called = 0;
case (c.getPure()) inside
[0:1]: called = 1;
[2:10]: $stop;
[0 : 1]: called = 1;
[2 : 10]: $stop;
default: $stop;
endcase
if (!called) $stop;

27
test_regress/t/t_class_type_param_upcast_all.v
View File

@ -23,7 +23,9 @@ class Unrelated;
int u_tag = 0;
endclass
class Fifo #(type T = Unrelated);
class Fifo #(
type T = Unrelated
);
T m_val;
task put(input T t);
m_val = t;
@ -35,12 +37,12 @@ endclass
module t;
Fifo #(Leaf) lf;
Fifo #(Mid) mf;
Fifo #(Mid) mf;
Fifo #(Base) bf;
Leaf l1, l2, l3;
Mid m1, m2;
Base b1, b2, b3;
Leaf l1, l2, l3;
Mid m1, m2;
Base b1, b2, b3;
initial begin
lf = new;
@ -48,35 +50,40 @@ module t;
bf = new;
// Output upcast Leaf -> Mid.
l1 = new; l1.seq = 1;
l1 = new;
l1.seq = 1;
lf.put(l1);
lf.get(m1);
if (m1 === null) $stop;
if (m1.seq !== 1) $stop;
// Output upcast Leaf -> Base (two levels).
l2 = new; l2.seq = 2;
l2 = new;
l2.seq = 2;
lf.put(l2);
lf.get(b1);
if (b1 === null) $stop;
if (b1.seq !== 2) $stop;
// Output upcast Mid -> Base.
m2 = new; m2.seq = 3;
m2 = new;
m2.seq = 3;
mf.put(m2);
mf.get(b2);
if (b2 === null) $stop;
if (b2.seq !== 3) $stop;
// Input upcast Leaf -> Base.
l3 = new; l3.seq = 4;
l3 = new;
l3.seq = 4;
bf.put(l3);
bf.get(b3);
if (b3 === null) $stop;
if (b3.seq !== 4) $stop;
// Same-type sanity.
m1 = new; m1.seq = 5;
m1 = new;
m1.seq = 5;
mf.put(m1);
mf.get(m2);
if (m2 === null) $stop;

6
test_regress/t/t_clocking_notiming.out
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@ -1,6 +1,6 @@
%Error-NOTIMING: t/t_clocking_notiming.v:11:8: Clocking output skew greater than #0 requires --timing
%Error-NOTIMING: t/t_clocking_notiming.v:11:5: Clocking output skew greater than #0 requires --timing
: ... note: In instance 't'
11 | output #1 out;
| ^~~~~~
11 | output #1 out;
| ^~~~~~
... For error description see https://verilator.org/warn/NOTIMING?v=latest
%Error: Exiting due to

10
test_regress/t/t_clocking_notiming.v
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@ -5,9 +5,9 @@
// SPDX-License-Identifier: CC0-1.0
module t;
logic clk;
logic out;
clocking cb @(posedge clk);
output #1 out;
endclocking
logic clk;
logic out;
clocking cb @(posedge clk);
output #1 out;
endclocking
endmodule

8
test_regress/t/t_dfg_3817.v
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@ -6,10 +6,10 @@
// SPDX-License-Identifier: CC0-1.0
module t (
output [2:0] c_b_a,
input a,
input b,
input c
output [2:0] c_b_a,
input a,
input b,
input c
);
assign c_b_a = {c, {b, a}};
endmodule

6
test_regress/t/t_dfg_3872.v
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@ -4,9 +4,9 @@
// SPDX-FileCopyrightText: 2023 Geza Lore
// SPDX-License-Identifier: CC0-1.0
module top(
input wire [1:0] i,
output wire [3:0] o
module top (
input wire [1:0] i,
output wire [3:0] o
);
assign o = 4'd2 ** i;
endmodule

17
test_regress/t/t_dfg_bin_to_one_hot.v
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@ -32,7 +32,12 @@ module t (
end
end
sub u_sub(clk, cyc, cntB, cntC);
sub u_sub (
clk,
cyc,
cntB,
cntC
);
// Should create decoder
wire [127:0] cntAOneHot = {
@ -585,16 +590,16 @@ module alt;
endmodule
module sub (
input wire clk,
input wire [31:0] cyc,
input wire [6:0] cntB,
input wire [6:0] cntC
input wire clk,
input wire [31:0] cyc,
input wire [6:0] cntB,
input wire [6:0] cntC
);
reg [6:0] cntB_q;
always @(posedge clk) cntB_q <= cntB;
alt u_alt();
alt u_alt ();
always @(posedge clk) u_alt.cntC_q <= cntC;
// Should create decoder

2
test_regress/t/t_display_string.v
View File

@ -22,5 +22,5 @@ module t;
// verilog_format: on
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule

13
test_regress/t/t_dpi_if_cond.v
View File

@ -6,21 +6,18 @@
// SPDX-FileCopyrightText: 2024 Antmicro
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
integer counter = 0;
import "DPI-C" context function int dpii_increment(inout int counter);
import "DPI-C" context function int dpii_increment(inout int counter);
function void func();
endfunction : func
always @(posedge clk) begin
if(dpii_increment(counter) == 1) begin
if (dpii_increment(counter) == 1) begin
// unreachable
func();

4
test_regress/t/t_emit_constw.v
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@ -10,8 +10,8 @@
// verilog_format: on
module t (
input clk
);
input clk
);
integer cyc = 0;
reg [63:0] crc;

12
test_regress/t/t_enum_huge_methods_bad.out
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@ -1,9 +1,9 @@
%Error: t/t_enum_huge_methods_bad.v:15:18: Value too wide for 64-bits expected in this context 160'h12344567abcd12344567abcd
15 | ELARGE = 160'h1234_4567_abcd_1234_4567_abcd
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%Error: t/t_enum_huge_methods_bad.v:13:14: Value too wide for 64-bits expected in this context 160'h12344567abcd12344567abcd
13 | ELARGE = 160'h1234_4567_abcd_1234_4567_abcd
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error-UNSUPPORTED: t/t_enum_huge_methods_bad.v:30:19: Unsupported: enum next/prev/name method on enum with > 64 bits
30 | $display(e.name);
| ^
%Error-UNSUPPORTED: t/t_enum_huge_methods_bad.v:28:16: Unsupported: enum next/prev/name method on enum with > 64 bits
28 | $display(e.name);
| ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

52
test_regress/t/t_enum_huge_methods_bad.v
View File

@ -4,36 +4,34 @@
// SPDX-FileCopyrightText: 2014 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
typedef enum logic [159:0] {
E01 = 160'h1,
ELARGE = 160'h1234_4567_abcd_1234_4567_abcd
} my_t;
typedef enum logic [159:0] {
E01 = 160'h1,
ELARGE = 160'h1234_4567_abcd_1234_4567_abcd
} my_t;
my_t e;
my_t e;
int cyc;
int cyc;
// Check runtime
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
e <= E01;
end
else if (cyc==1) begin
$display(e.name);
e <= ELARGE;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
// Check runtime
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 0) begin
// Setup
e <= E01;
end
else if (cyc == 1) begin
$display(e.name);
e <= ELARGE;
end
else if (cyc == 99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule

56
test_regress/t/t_event_dynamic_wait.v
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@ -5,41 +5,41 @@
// SPDX-License-Identifier: CC0-1.0
class EventHolder;
event ev;
time t_wait = '0;
event ev;
time t_wait = '0;
task wait_once;
@ev;
t_wait = $time;
endtask
task wait_once;
@ev;
t_wait = $time;
endtask
endclass
module t;
EventHolder h;
EventHolder h;
initial begin
h = new;
initial begin
h = new;
// Leave the event in the fired state before a class-method event control
// starts. Dynamic waits must pre-clear this stale state before evaluating.
->h.ev;
#10;
// Leave the event in the fired state before a class-method event control
// starts. Dynamic waits must pre-clear this stale state before evaluating.
->h.ev;
#10;
fork
begin
#10 ->h.ev;
end
begin
h.wait_once;
end
join
if (h.t_wait != 20) begin
$display("%%Error: wait time=%0d expected=20", h.t_wait);
$stop;
fork
begin
#10->h.ev;
end
begin
h.wait_once;
end
join
$write("*-* All Finished *-*\n");
$finish;
end
if (h.t_wait != 20) begin
$display("%%Error: wait time=%0d expected=20", h.t_wait);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

2
test_regress/t/t_flag_compiler.v
View File

@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
module t (
input clk
input clk
);
integer cyc = 0;

51
test_regress/t/t_flag_define.v
View File

@ -27,95 +27,112 @@ module t;
`ifdef D1A
if (`STRINGIFY(`D4B) !== "") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
$write("%%Error: Missing define\n");
$stop;
`endif
`ifdef D2A
if (`STRINGIFY(`D2A) !== "VALA") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
$write("%%Error: Missing define\n");
$stop;
`endif
`ifdef D3A
if (`STRINGIFY(`D4B) !== "") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
$write("%%Error: Missing define\n");
$stop;
`endif
`ifdef D3B
if (`STRINGIFY(`D4B) !== "") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
$write("%%Error: Missing define\n");
$stop;
`endif
`ifdef D4A
if (`STRINGIFY(`D4A) !== "VALA") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
$write("%%Error: Missing define\n");
$stop;
`endif
`ifdef D4B
if (`STRINGIFY(`D4B) !== "") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
$write("%%Error: Missing define\n");
$stop;
`endif
`ifdef D5A
if (`STRINGIFY(`D5A) !== "VALA") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
$write("%%Error: Missing define\n");
$stop;
`endif
`ifdef D5A
if (`STRINGIFY(`D5B) !== "VALB") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
$write("%%Error: Missing define\n");
$stop;
`endif
`ifdef STRING1
if (`STRING1 !== "New String") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
$write("%%Error: Missing define\n");
$stop;
`endif
`ifdef STRING2
if (`STRING2 !== "New String") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
$write("%%Error: Missing define\n");
$stop;
`endif
`ifdef STRING3
if (`STRING3 !== "New String") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
$write("%%Error: Missing define\n");
$stop;
`endif
`ifdef LIT1
if (`STRINGIFY(`LIT1) !== "32'h600D600D") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
$write("%%Error: Missing define\n");
$stop;
`endif
`ifdef LIT2
if (`STRINGIFY(`LIT2) !== "32'h600D600D") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
$write("%%Error: Missing define\n");
$stop;
`endif
`ifdef LIT3
if (`STRINGIFY(`LIT3) !== "32'h600D600D") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
$write("%%Error: Missing define\n");
$stop;
`endif
`ifndef CMD_DEF
$write("%%Error: Missing define\n"); $stop;
$write("%%Error: Missing define\n");
$stop;
`endif
`ifndef CMD_DEF2
$write("%%Error: Missing define\n"); $stop;
$write("%%Error: Missing define\n");
$stop;
`endif
`ifdef CMD_UNDEF
$write("%%Error: Extra define\n"); $stop;
$write("%%Error: Extra define\n");
$stop;
`endif
$write("*-* All Finished *-*\n");

2
test_regress/t/t_flag_parameter_hier.v
View File

@ -10,7 +10,7 @@
// verilog_format: on
module t (
input clk
input clk
);
u u ();

6
test_regress/t/t_force.v
View File

@ -13,7 +13,7 @@
module t_assert;
logic clk;
logic zeroize;
logic [7:0] key_mem [0:0];
logic [7:0] key_mem[0:0];
assert property (@(posedge clk) zeroize |=> (key_mem[0] == 0));
initial force zeroize = 0;
endmodule
@ -22,7 +22,7 @@ module t (
input clk
);
t_assert t_assert_i();
t_assert t_assert_i ();
integer cyc = 0;
localparam logic [95:0] WIDE_INIT = 96'h12345678_9abcdef0_13579bdf;
@ -32,7 +32,7 @@ module t (
tri [3:0] bus = in;
logic [95:0] wide_src;
wire [95:0] wide_bus = wide_src;
logic [7:0] unpacked [0:3];
logic [7:0] unpacked[0:3];
int never_driven;
int never_forced;

23
test_regress/t/t_force_assign.v
View File

@ -10,14 +10,15 @@
// verilog_format: on
module t;
reg [1:0] a=0, b=1;
reg [1:0] a = 0, b = 1;
reg [1:0] r;
initial begin
r = 2'b00;
assign r = 2'b01;
`checkb(r, 2'b01)
r = 2'b00; // ignored
#1; `checkb(r, 2'b01)
r = 2'b00; // ignored
#1;
`checkb(r, 2'b01)
deassign r;
`checkb(r, 2'b01)
r = 2'b00;
@ -29,12 +30,16 @@ module t;
a = 2'b00;
`checkb(r, 2'b00)
force r = a + b;
a = 2'b00; b = 2'b00;
#1; `checkb(r, 2'b00)
a = 2'b01; b = 2'b01;
#1; `checkb(r, 2'b10)
assign r = b; // covered
r = 2'b11; // ignored
a = 2'b00;
b = 2'b00;
#1;
`checkb(r, 2'b00)
a = 2'b01;
b = 2'b01;
#1;
`checkb(r, 2'b10)
assign r = b; // covered
r = 2'b11; // ignored
`checkb(r, 2'b10)
release r;
`checkb(r, 2'b01)

4
test_regress/t/t_force_chained.v
View File

@ -4,10 +4,10 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
// verilog_format: on
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
// verilog_format: off
// verilog_format: on
module t;
reg [1:0] a;

6
test_regress/t/t_fork_join_none_class_cap.v
View File

@ -17,8 +17,7 @@ class Foo;
#20 begin
m_member++;
$display("this's m_member: %0d m_en: %s", m_member, m_en.name());
if (m_member != 3)
$stop;
if (m_member != 3) $stop;
->evt1;
end
#10 begin
@ -33,8 +32,7 @@ class Foo;
begin
foo.m_member++;
$display("foo's m_member: %0d m_en: %s", foo.m_member, foo.m_en.name());
if (foo.m_member != 2)
$stop;
if (foo.m_member != 2) $stop;
end
join_none
endtask

10
test_regress/t/t_fork_join_none_virtual.v
View File

@ -17,8 +17,7 @@ class Foo;
#20 begin
m_member++;
$display("this's m_member: %0d m_en: %s", m_member, m_en.name());
if (m_member != 3)
$stop;
if (m_member != 3) $stop;
->evt1;
end
#10 begin
@ -33,15 +32,16 @@ class Foo;
begin
foo.m_member++;
$display("foo's m_member: %0d m_en: %s", foo.m_member, foo.m_en.name());
if (foo.m_member != 2)
$stop;
if (foo.m_member != 2) $stop;
end
join_none
endtask
endclass
class Subfoo extends Foo;
virtual task do_something();#5;endtask
virtual task do_something();
#5;
endtask
endclass
module t;

4
test_regress/t/t_func_named.v
View File

@ -11,8 +11,8 @@
module t;
function automatic int f( int j = 1, int s = 0 );
return (j<<16) | s;
function automatic int f(int j = 1, int s = 0);
return (j << 16) | s;
endfunction
initial begin

2
test_regress/t/t_func_twocall.v
View File

@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
module t (
input clk
input clk
);
reg [7:0] crc;

6
test_regress/t/t_genvar_misuse_bad.v
View File

@ -7,9 +7,9 @@
module top (
output logic [1:0] q,
input logic [1:0] d,
input logic clk
);
input logic [1:0] d,
input logic clk
);
genvar i;
assign q[i] = d[i]; // <--- Error: Misusing genvar i

6
test_regress/t/t_hier_block_import/t_hier_block_import_subA.v
View File

@ -6,6 +6,8 @@
// SPDX-FileCopyrightText: 2024 Antmicro
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
module subA (output bit [31:0] out); /*verilator hier_block*/
subsub subsub(.out(out));
module subA (
output bit [31:0] out
); /*verilator hier_block*/
subsub subsub (.out(out));
endmodule

4
test_regress/t/t_hier_block_import/t_hier_block_import_subB.v
View File

@ -7,6 +7,8 @@
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
// Note: no hier_block pragma here to validate partial hier_block design
module subB (output bit [31:0] out);
module subB (
output bit [31:0] out
);
assign out = `VALUE_B;
endmodule

12
test_regress/t/t_initialstatic_circ.v
View File

@ -9,21 +9,19 @@ package pkg;
function int unsigned func();
int unsigned local_id;
local_id = id + 1;
local_id = id + 1;
id = local_id;
return local_id;
endfunction : func
endpackage
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
import pkg::*;
int unsigned func_id = func();
always @ (posedge clk) begin
always @(posedge clk) begin
$display(id);
$write("*-* All Finished *-*\n");
$finish;

2
test_regress/t/t_interface_func_no_paren.v
View File

@ -19,7 +19,7 @@ class cls;
endclass
module t;
intf intf();
intf intf ();
cls c;
initial begin
intf.status = 'hdeadbeef;

8
test_regress/t/t_interface_virtual_sched_act.v
View File

@ -11,7 +11,7 @@ endinterface
module t_sched_act;
logic clk = 0;
integer cyc = 0;
Bus intf();
Bus intf ();
virtual Bus vif = intf;
logic [15:0] data;
@ -22,9 +22,9 @@ module t_sched_act;
// Finish on negedge so that $finish is last
always @(negedge clk)
if (cyc >= 6) begin
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
always @(posedge clk or data) begin
if (cyc == 1) intf.data <= 'hdead;

4
test_regress/t/t_interface_virtual_sched_ico.v
View File

@ -15,8 +15,8 @@ module top;
logic [31:0] inc2 = 0;
int cyc = 0;
If intf1();
If intf2();
If intf1 ();
If intf2 ();
virtual If vif1 = intf1;
virtual If vif2 = intf2;

24
test_regress/t/t_interface_virtual_sched_nba.v
View File

@ -20,9 +20,9 @@ module t;
logic clk = 0;
integer cyc = 0;
Bus1 intf1();
Bus2 intf2();
Bus3 intf3();
Bus1 intf1 ();
Bus2 intf2 ();
Bus3 intf3 ();
virtual Bus1 vif1 = intf1;
virtual Bus2 vif2 = intf2;
virtual Bus3 vif3 = intf3;
@ -35,18 +35,12 @@ module t;
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 1)
vif1.data = 'hdead;
else if (cyc == 2)
data = vif1.data;
else if (cyc == 3)
vif1.data = 'hbeef;
else if (cyc == 4)
data = vif1.data;
else if (cyc == 5)
intf3.data <= 'hface;
else if (cyc == 6)
intf3.data <= 'hcafe;
if (cyc == 1) vif1.data = 'hdead;
else if (cyc == 2) data = vif1.data;
else if (cyc == 3) vif1.data = 'hbeef;
else if (cyc == 4) data = vif1.data;
else if (cyc == 5) intf3.data <= 'hface;
else if (cyc == 6) intf3.data <= 'hcafe;
end
// Finish on negedge so that $finish is last

314
test_regress/t/t_json_only_flat_vlvbound.out
View File

@ -2,348 +2,348 @@
"modulesp": [
{"type":"MODULE","name":"$root","addr":"(F)","loc":"d,7:8,7:21","origName":"$root","verilogName":"$root","level":1,"modPublic":true,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"i_a","addr":"(G)","loc":"d,9:25,9:28","dtypep":"(H)","origName":"i_a","verilogName":"i_a","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"i_b","addr":"(I)","loc":"d,10:25,10:28","dtypep":"(H)","origName":"i_b","verilogName":"i_b","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"o_a","addr":"(J)","loc":"d,11:25,11:28","dtypep":"(K)","origName":"o_a","verilogName":"o_a","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"o_b","addr":"(L)","loc":"d,12:25,12:28","dtypep":"(K)","origName":"o_b","verilogName":"o_b","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"vlvbound_test.i_a","addr":"(M)","loc":"d,9:25,9:28","dtypep":"(H)","origName":"i_a","verilogName":"i_a","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"vlvbound_test.i_b","addr":"(N)","loc":"d,10:25,10:28","dtypep":"(H)","origName":"i_b","verilogName":"i_b","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"vlvbound_test.o_a","addr":"(O)","loc":"d,11:25,11:28","dtypep":"(K)","origName":"o_a","verilogName":"o_a","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"vlvbound_test.o_b","addr":"(P)","loc":"d,12:25,12:28","dtypep":"(K)","origName":"o_b","verilogName":"o_b","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"i_a","addr":"(G)","loc":"d,8:24,8:27","dtypep":"(H)","origName":"i_a","verilogName":"i_a","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"i_b","addr":"(I)","loc":"d,9:24,9:27","dtypep":"(H)","origName":"i_b","verilogName":"i_b","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"o_a","addr":"(J)","loc":"d,10:24,10:27","dtypep":"(K)","origName":"o_a","verilogName":"o_a","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"o_b","addr":"(L)","loc":"d,11:24,11:27","dtypep":"(K)","origName":"o_b","verilogName":"o_b","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"vlvbound_test.i_a","addr":"(M)","loc":"d,8:24,8:27","dtypep":"(H)","origName":"i_a","verilogName":"i_a","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"vlvbound_test.i_b","addr":"(N)","loc":"d,9:24,9:27","dtypep":"(H)","origName":"i_b","verilogName":"i_b","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"vlvbound_test.o_a","addr":"(O)","loc":"d,10:24,10:27","dtypep":"(K)","origName":"o_a","verilogName":"o_a","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"vlvbound_test.o_b","addr":"(P)","loc":"d,11:24,11:27","dtypep":"(K)","origName":"o_b","verilogName":"o_b","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"TOPSCOPE","name":"","addr":"(E)","loc":"d,7:8,7:21","senTreesp": [],
"scopep": [
{"type":"SCOPE","name":"TOP","addr":"(Q)","loc":"d,7:8,7:21","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(F)",
"varsp": [
{"type":"VARSCOPE","name":"i_a","addr":"(R)","loc":"d,9:25,9:28","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(G)"},
{"type":"VARSCOPE","name":"i_b","addr":"(S)","loc":"d,10:25,10:28","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(I)"},
{"type":"VARSCOPE","name":"o_a","addr":"(T)","loc":"d,11:25,11:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(J)"},
{"type":"VARSCOPE","name":"o_b","addr":"(U)","loc":"d,12:25,12:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(L)"},
{"type":"VARSCOPE","name":"vlvbound_test.i_a","addr":"(V)","loc":"d,9:25,9:28","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(M)"},
{"type":"ALWAYS","name":"","addr":"(W)","loc":"d,9:25,9:28","keyword":"cont_assign","sentreep": [],
{"type":"VARSCOPE","name":"i_a","addr":"(R)","loc":"d,8:24,8:27","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(G)"},
{"type":"VARSCOPE","name":"i_b","addr":"(S)","loc":"d,9:24,9:27","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(I)"},
{"type":"VARSCOPE","name":"o_a","addr":"(T)","loc":"d,10:24,10:27","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(J)"},
{"type":"VARSCOPE","name":"o_b","addr":"(U)","loc":"d,11:24,11:27","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(L)"},
{"type":"VARSCOPE","name":"vlvbound_test.i_a","addr":"(V)","loc":"d,8:24,8:27","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(M)"},
{"type":"ALWAYS","name":"","addr":"(W)","loc":"d,8:24,8:27","keyword":"cont_assign","sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(X)","loc":"d,9:25,9:28","dtypep":"(H)",
{"type":"ASSIGNW","name":"","addr":"(X)","loc":"d,8:24,8:27","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"i_a","addr":"(Y)","loc":"d,9:25,9:28","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(R)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"i_a","addr":"(Y)","loc":"d,8:24,8:27","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(R)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"vlvbound_test.i_a","addr":"(Z)","loc":"d,9:25,9:28","dtypep":"(H)","access":"WR","varp":"(M)","varScopep":"(V)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"vlvbound_test.i_a","addr":"(Z)","loc":"d,8:24,8:27","dtypep":"(H)","access":"WR","varp":"(M)","varScopep":"(V)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]},
{"type":"VARSCOPE","name":"vlvbound_test.i_b","addr":"(AB)","loc":"d,10:25,10:28","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(N)"},
{"type":"ALWAYS","name":"","addr":"(BB)","loc":"d,10:25,10:28","keyword":"cont_assign","sentreep": [],
{"type":"VARSCOPE","name":"vlvbound_test.i_b","addr":"(AB)","loc":"d,9:24,9:27","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(N)"},
{"type":"ALWAYS","name":"","addr":"(BB)","loc":"d,9:24,9:27","keyword":"cont_assign","sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(CB)","loc":"d,10:25,10:28","dtypep":"(H)",
{"type":"ASSIGNW","name":"","addr":"(CB)","loc":"d,9:24,9:27","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"i_b","addr":"(DB)","loc":"d,10:25,10:28","dtypep":"(H)","access":"RD","varp":"(I)","varScopep":"(S)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"i_b","addr":"(DB)","loc":"d,9:24,9:27","dtypep":"(H)","access":"RD","varp":"(I)","varScopep":"(S)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"vlvbound_test.i_b","addr":"(EB)","loc":"d,10:25,10:28","dtypep":"(H)","access":"WR","varp":"(N)","varScopep":"(AB)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"vlvbound_test.i_b","addr":"(EB)","loc":"d,9:24,9:27","dtypep":"(H)","access":"WR","varp":"(N)","varScopep":"(AB)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]},
{"type":"VARSCOPE","name":"vlvbound_test.o_a","addr":"(FB)","loc":"d,11:25,11:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(O)"},
{"type":"ALWAYS","name":"","addr":"(GB)","loc":"d,11:25,11:28","keyword":"cont_assign","sentreep": [],
{"type":"VARSCOPE","name":"vlvbound_test.o_a","addr":"(FB)","loc":"d,10:24,10:27","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(O)"},
{"type":"ALWAYS","name":"","addr":"(GB)","loc":"d,10:24,10:27","keyword":"cont_assign","sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(HB)","loc":"d,11:25,11:28","dtypep":"(K)",
{"type":"ASSIGNW","name":"","addr":"(HB)","loc":"d,10:24,10:27","dtypep":"(K)",
"rhsp": [
{"type":"VARREF","name":"o_a","addr":"(IB)","loc":"d,11:25,11:28","dtypep":"(K)","access":"RD","varp":"(J)","varScopep":"(T)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"o_a","addr":"(IB)","loc":"d,10:24,10:27","dtypep":"(K)","access":"RD","varp":"(J)","varScopep":"(T)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"vlvbound_test.o_a","addr":"(JB)","loc":"d,11:25,11:28","dtypep":"(K)","access":"WR","varp":"(O)","varScopep":"(FB)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"vlvbound_test.o_a","addr":"(JB)","loc":"d,10:24,10:27","dtypep":"(K)","access":"WR","varp":"(O)","varScopep":"(FB)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]},
{"type":"VARSCOPE","name":"vlvbound_test.o_b","addr":"(KB)","loc":"d,12:25,12:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(P)"},
{"type":"ALWAYS","name":"","addr":"(LB)","loc":"d,12:25,12:28","keyword":"cont_assign","sentreep": [],
{"type":"VARSCOPE","name":"vlvbound_test.o_b","addr":"(KB)","loc":"d,11:24,11:27","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(P)"},
{"type":"ALWAYS","name":"","addr":"(LB)","loc":"d,11:24,11:27","keyword":"cont_assign","sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(MB)","loc":"d,12:25,12:28","dtypep":"(K)",
{"type":"ASSIGNW","name":"","addr":"(MB)","loc":"d,11:24,11:27","dtypep":"(K)",
"rhsp": [
{"type":"VARREF","name":"o_b","addr":"(NB)","loc":"d,12:25,12:28","dtypep":"(K)","access":"RD","varp":"(L)","varScopep":"(U)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"o_b","addr":"(NB)","loc":"d,11:24,11:27","dtypep":"(K)","access":"RD","varp":"(L)","varScopep":"(U)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"vlvbound_test.o_b","addr":"(OB)","loc":"d,12:25,12:28","dtypep":"(K)","access":"WR","varp":"(P)","varScopep":"(KB)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"vlvbound_test.o_b","addr":"(OB)","loc":"d,11:24,11:27","dtypep":"(K)","access":"WR","varp":"(P)","varScopep":"(KB)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(PB)","loc":"d,15:34,15:37","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(QB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(RB)","loc":"d,15:57,15:60","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(SB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(TB)","loc":"d,16:17,16:20","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(UB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(VB)","loc":"d,17:13,17:14","dtypep":"(WB)","isTrace":true,"scopep":"(Q)","varp":"(XB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(YB)","loc":"d,15:34,15:37","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(ZB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(AC)","loc":"d,15:57,15:60","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(BC)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(CC)","loc":"d,16:17,16:20","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(DC)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(EC)","loc":"d,17:13,17:14","dtypep":"(WB)","isTrace":true,"scopep":"(Q)","varp":"(FC)"}
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(PB)","loc":"d,14:34,14:37","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(QB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(RB)","loc":"d,14:57,14:60","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(SB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(TB)","loc":"d,15:17,15:20","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(UB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(VB)","loc":"d,16:13,16:14","dtypep":"(WB)","isTrace":true,"scopep":"(Q)","varp":"(XB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(YB)","loc":"d,14:34,14:37","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(ZB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(AC)","loc":"d,14:57,14:60","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(BC)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(CC)","loc":"d,15:17,15:20","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(DC)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(EC)","loc":"d,16:13,16:14","dtypep":"(WB)","isTrace":true,"scopep":"(Q)","varp":"(FC)"}
],
"blocksp": [
{"type":"ALWAYS","name":"","addr":"(GC)","loc":"d,24:14,24:15","keyword":"cont_assign","sentreep": [],
{"type":"ALWAYS","name":"","addr":"(GC)","loc":"d,23:14,23:15","keyword":"cont_assign","sentreep": [],
"stmtsp": [
{"type":"COMMENT","name":"Function: foo","addr":"(HC)","loc":"d,24:16,24:19"},
{"type":"ASSIGN","name":"","addr":"(IC)","loc":"d,24:20,24:23","dtypep":"(H)",
{"type":"COMMENT","name":"Function: foo","addr":"(HC)","loc":"d,23:16,23:19"},
{"type":"ASSIGN","name":"","addr":"(IC)","loc":"d,23:20,23:23","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"i_a","addr":"(JC)","loc":"d,24:20,24:23","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(R)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"i_a","addr":"(JC)","loc":"d,23:20,23:23","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(R)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(KC)","loc":"d,15:57,15:60","dtypep":"(H)","access":"WR","varp":"(SB)","varScopep":"(RB)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(KC)","loc":"d,14:57,14:60","dtypep":"(H)","access":"WR","varp":"(SB)","varScopep":"(RB)","classOrPackagep":"UNLINKED"}
],"timingControlp": []},
{"type":"ASSIGN","name":"","addr":"(LC)","loc":"d,15:34,15:37","dtypep":"(K)",
{"type":"ASSIGN","name":"","addr":"(LC)","loc":"d,14:34,14:37","dtypep":"(K)",
"rhsp": [
{"type":"CRESET","name":"","addr":"(MC)","loc":"d,15:34,15:37","dtypep":"(K)"}
{"type":"CRESET","name":"","addr":"(MC)","loc":"d,14:34,14:37","dtypep":"(K)"}
],
"lhsp": [
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(NC)","loc":"d,15:34,15:37","dtypep":"(K)","access":"WR","varp":"(QB)","varScopep":"(PB)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(NC)","loc":"d,14:34,14:37","dtypep":"(K)","access":"WR","varp":"(QB)","varScopep":"(PB)","classOrPackagep":"UNLINKED"}
],"timingControlp": []},
{"type":"ASSIGN","name":"","addr":"(OC)","loc":"d,16:17,16:20","dtypep":"(K)",
{"type":"ASSIGN","name":"","addr":"(OC)","loc":"d,15:17,15:20","dtypep":"(K)",
"rhsp": [
{"type":"CRESET","name":"","addr":"(PC)","loc":"d,16:17,16:20","dtypep":"(K)"}
{"type":"CRESET","name":"","addr":"(PC)","loc":"d,15:17,15:20","dtypep":"(K)"}
],
"lhsp": [
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(QC)","loc":"d,16:17,16:20","dtypep":"(K)","access":"WR","varp":"(UB)","varScopep":"(TB)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(QC)","loc":"d,15:17,15:20","dtypep":"(K)","access":"WR","varp":"(UB)","varScopep":"(TB)","classOrPackagep":"UNLINKED"}
],"timingControlp": []},
{"type":"ASSIGN","name":"","addr":"(RC)","loc":"d,17:13,17:14","dtypep":"(WB)",
{"type":"ASSIGN","name":"","addr":"(RC)","loc":"d,16:13,16:14","dtypep":"(WB)",
"rhsp": [
{"type":"CRESET","name":"","addr":"(SC)","loc":"d,17:13,17:14","dtypep":"(WB)"}
{"type":"CRESET","name":"","addr":"(SC)","loc":"d,16:13,16:14","dtypep":"(WB)"}
],
"lhsp": [
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(TC)","loc":"d,17:13,17:14","dtypep":"(WB)","access":"WR","varp":"(XB)","varScopep":"(VB)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(TC)","loc":"d,16:13,16:14","dtypep":"(WB)","access":"WR","varp":"(XB)","varScopep":"(VB)","classOrPackagep":"UNLINKED"}
],"timingControlp": []},
{"type":"ASSIGN","name":"","addr":"(UC)","loc":"d,18:11,18:12","dtypep":"(WB)",
{"type":"ASSIGN","name":"","addr":"(UC)","loc":"d,17:12,17:13","dtypep":"(WB)",
"rhsp": [
{"type":"CONST","name":"32'sh0","addr":"(VC)","loc":"d,18:12,18:13","dtypep":"(WC)"}
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{"type":"SEL","name":"","addr":"(LF)","loc":"d,18:20,18:21","dtypep":"(KD)","widthConst":2,"declRange":"[15:0]","declElWidth":1,
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{"type":"ADD","name":"","addr":"(YF)","loc":"d,17:25,17:27","dtypep":"(CE)",
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{"type":"CONST","name":"32'h1","addr":"(ZF)","loc":"d,17:25,17:27","dtypep":"(TD)"}
],
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],"timingControlp": []},
{"type":"ASSIGNW","name":"","addr":"(FG)","loc":"d,25:14,25:15","dtypep":"(K)",
{"type":"ASSIGNW","name":"","addr":"(FG)","loc":"d,24:14,24:15","dtypep":"(K)",
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{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(GG)","loc":"d,24:16,24:19","dtypep":"(K)","access":"RD","varp":"(ZB)","varScopep":"(YB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"o_b","addr":"(HG)","loc":"d,25:10,25:13","dtypep":"(K)","access":"WR","varp":"(L)","varScopep":"(U)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"o_b","addr":"(HG)","loc":"d,24:10,24:13","dtypep":"(K)","access":"WR","varp":"(L)","varScopep":"(U)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]}
],"inlinesp": []}
]},
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(QB)","loc":"d,15:34,15:37","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__0__Vfuncout","verilogName":"__Vfunc_vlvbound_test.foo__0__Vfuncout","direction":"NONE","lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
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{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(BC)","loc":"d,14:57,14:60","dtypep":"(H)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__val","verilogName":"__Vfunc_vlvbound_test.foo__1__val","direction":"NONE","lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(DC)","loc":"d,15:17,15:20","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__ret","verilogName":"__Vfunc_vlvbound_test.foo__1__ret","direction":"NONE","lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(FC)","loc":"d,16:13,16:14","dtypep":"(WB)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__i","verilogName":"__Vfunc_vlvbound_test.foo__1__i","direction":"NONE","lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
]}
],"filesp": [],
"miscsp": [
{"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"UNLINKED",
"typesp": [
{"type":"BASICDTYPE","name":"bit","addr":"(BD)","loc":"d,18:18,18:19","dtypep":"(BD)","keyword":"bit","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"bit","addr":"(ID)","loc":"d,19:34,19:39","dtypep":"(ID)","keyword":"bit","range":"1:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(FD)","loc":"d,19:31,19:33","dtypep":"(FD)","keyword":"logic","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(H)","loc":"d,9:11,9:16","dtypep":"(H)","keyword":"logic","range":"15:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(K)","loc":"d,11:12,11:17","dtypep":"(K)","keyword":"logic","range":"6:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"integer","addr":"(WB)","loc":"d,17:5,17:12","dtypep":"(WB)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(PD)","loc":"d,18:18,18:19","dtypep":"(PD)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(XD)","loc":"d,19:10,19:11","dtypep":"(XD)","keyword":"logic","range":"2:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"bit","addr":"(TD)","loc":"d,19:11,19:12","dtypep":"(TD)","keyword":"bit","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(KD)","loc":"d,19:20,19:21","dtypep":"(KD)","keyword":"logic","range":"1:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(ND)","loc":"d,19:20,19:21","dtypep":"(ND)","keyword":"logic","range":"3:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(CE)","loc":"d,18:24,18:26","dtypep":"(CE)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"bit","addr":"(WC)","loc":"d,18:12,18:13","dtypep":"(WC)","keyword":"bit","range":"31:0","generic":true,"signed":true,"rangep": []}
{"type":"BASICDTYPE","name":"bit","addr":"(BD)","loc":"d,17:19,17:20","dtypep":"(BD)","keyword":"bit","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"bit","addr":"(ID)","loc":"d,18:32,18:37","dtypep":"(ID)","keyword":"bit","range":"1:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(FD)","loc":"d,18:29,18:31","dtypep":"(FD)","keyword":"logic","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(H)","loc":"d,8:11,8:16","dtypep":"(H)","keyword":"logic","range":"15:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(K)","loc":"d,10:12,10:17","dtypep":"(K)","keyword":"logic","range":"6:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"integer","addr":"(WB)","loc":"d,16:5,16:12","dtypep":"(WB)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(PD)","loc":"d,17:19,17:20","dtypep":"(PD)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(XD)","loc":"d,18:10,18:11","dtypep":"(XD)","keyword":"logic","range":"2:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"bit","addr":"(TD)","loc":"d,18:11,18:12","dtypep":"(TD)","keyword":"bit","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(KD)","loc":"d,18:20,18:21","dtypep":"(KD)","keyword":"logic","range":"1:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(ND)","loc":"d,18:20,18:21","dtypep":"(ND)","keyword":"logic","range":"3:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(CE)","loc":"d,17:25,17:27","dtypep":"(CE)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"bit","addr":"(WC)","loc":"d,17:14,17:15","dtypep":"(WC)","keyword":"bit","range":"31:0","generic":true,"signed":true,"rangep": []}
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [

17
test_regress/t/t_json_only_flat_vlvbound.v
View File

@ -4,19 +4,18 @@
// SPDX-FileCopyrightText: 2012 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module vlvbound_test
(
input logic [15:0] i_a,
input logic [15:0] i_b,
output logic [6:0] o_a,
output logic [6:0] o_b
);
module vlvbound_test (
input logic [15:0] i_a,
input logic [15:0] i_b,
output logic [6:0] o_a,
output logic [6:0] o_b
);
function automatic logic [6:0] foo(input logic [15:0] val);
logic [6:0] ret;
integer i;
for (i=0 ; i < 7; i++) begin
ret[i] = (val[i*2 +: 2] == 2'b00);
for (i = 0; i < 7; i++) begin
ret[i] = (val[i*2+:2] == 2'b00);
end
return ret;
endfunction

4
test_regress/t/t_json_only_output.out
View File

@ -2,13 +2,13 @@
"modulesp": [
{"type":"MODULE","name":"m","addr":"(E)","loc":"d,7:8,7:9","origName":"m","verilogName":"m","level":1,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"clk","addr":"(F)","loc":"d,8:10,8:13","dtypep":"(G)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
{"type":"VAR","name":"clk","addr":"(F)","loc":"d,8:11,8:14","dtypep":"(G)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
]}
],"filesp": [],
"miscsp": [
{"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"UNLINKED",
"typesp": [
{"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,8:10,8:13","dtypep":"(G)","keyword":"logic","generic":true,"rangep": []}
{"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,8:11,8:14","dtypep":"(G)","keyword":"logic","generic":true,"rangep": []}
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [

5
test_regress/t/t_json_only_output.v
View File

@ -4,7 +4,8 @@
// SPDX-FileCopyrightText: 2019 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module m
(input clk); // verilator tag foo_op
module m (
input clk
); // verilator tag foo_op
endmodule

12
test_regress/t/t_lint_block_redecl_bad.out
View File

@ -1,8 +1,8 @@
%Error: t/t_lint_block_redecl_bad.v:17:25: Duplicate declaration of block: 'COMB'
17 | for(i=0; i<9; i++ ) begin: COMB
| ^~~~~
t/t_lint_block_redecl_bad.v:14:26: ... Location of original declaration
14 | for(i=0; i<10; i++ ) begin: COMB
| ^~~~~
%Error: t/t_lint_block_redecl_bad.v:17:29: Duplicate declaration of block: 'COMB'
17 | for (i = 0; i < 9; i++) begin : COMB
| ^~~~~
t/t_lint_block_redecl_bad.v:14:30: ... Location of original declaration
14 | for (i = 0; i < 10; i++) begin : COMB
| ^~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

4
test_regress/t/t_lint_block_redecl_bad.v
View File

@ -11,10 +11,10 @@ module t;
always_comb begin
integer i;
for(i=0; i<10; i++ ) begin: COMB
for (i = 0; i < 10; i++) begin : COMB
end
for(i=0; i<9; i++ ) begin: COMB
for (i = 0; i < 9; i++) begin : COMB
end
end
endmodule

4
test_regress/t/t_lint_caseincomplete_bad.out
View File

@ -1,5 +1,5 @@
%Warning-CASEINCOMPLETE: t/t_lint_caseincomplete_bad.v:15:5: Case values incompletely covered (example pattern 0x1)
15 | case (i)
%Warning-CASEINCOMPLETE: t/t_lint_caseincomplete_bad.v:12:5: Case values incompletely covered (example pattern 0x1)
12 | case (i)
| ^~~~
... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=latest
... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message.

9
test_regress/t/t_lint_caseincomplete_bad.v
View File

@ -4,12 +4,9 @@
// SPDX-FileCopyrightText: 2020 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
i
);
input [1:0] i;
module t (
input [1:0] i
);
always_comb begin
case (i)

4
test_regress/t/t_lint_comb_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_lint_comb_bad.v:14:3: Event control statements not legal under always_comb (IEEE 1800-2023 9.2.2.2.2)
%Error: t/t_lint_comb_bad.v:11:3: Event control statements not legal under always_comb (IEEE 1800-2023 9.2.2.2.2)
: ... Suggest use a normal 'always'
14 | always_comb @(*) begin
11 | always_comb @(*) begin
| ^~~~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

9
test_regress/t/t_lint_comb_bad.v
View File

@ -4,12 +4,9 @@
// SPDX-FileCopyrightText: 2017 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
always_comb @(*) begin
$stop;

4
test_regress/t/t_lint_const_func_gen_bad.v
View File

@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
module t;
if (1) begin: GenConstFunc
if (1) begin : GenConstFunc
// IEEE 1800-2023 13.4.3, constant functions shall not be declared inside a
//generate block
function automatic bit constFunc();
@ -13,5 +13,5 @@ module t;
endfunction
localparam PARAM = constFunc();
end
end
endmodule

4
test_regress/t/t_lint_contassreg_bad.out
View File

@ -1,6 +1,6 @@
%Error-CONTASSREG: t/t_lint_contassreg_bad.v:14:10: Continuous assignment to reg, perhaps intended wire (IEEE 1364-2005 6.1; Verilog only, legal in SV): 'r'
%Error-CONTASSREG: t/t_lint_contassreg_bad.v:16:10: Continuous assignment to reg, perhaps intended wire (IEEE 1364-2005 6.1; Verilog only, legal in SV): 'r'
: ... note: In instance 't'
14 | assign r = 1'b0;
16 | assign r = 1'b0;
| ^
... For error description see https://verilator.org/warn/CONTASSREG?v=latest
%Error: Exiting due to

4
test_regress/t/t_lint_contassreg_bad.v
View File

@ -5,7 +5,9 @@
// SPDX-License-Identifier: CC0-1.0
module t(r);
module t (
r
);
output r;

4
test_regress/t/t_lint_ftask_output_assign_bad.v
View File

@ -5,8 +5,8 @@
// SPDX-License-Identifier: CC0-1.0
module t (
input logic in,
output wire wire_out,
input logic in,
output wire wire_out,
output logic reg_out
);
function void set_f(output set_out, input set_in);

4
test_regress/t/t_lint_literal_bad.out
View File

@ -1,5 +1,5 @@
%Warning-WIDTHTRUNC: t/t_lint_literal_bad.v:10:31: Value too large for 8 bit number: 256
10 | localparam the_localparam = 8'd256;
%Warning-WIDTHTRUNC: t/t_lint_literal_bad.v:9:31: Value too large for 8 bit number: 256
9 | localparam the_localparam = 8'd256;
| ^~~~~~
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.

3
test_regress/t/t_lint_literal_bad.v
View File

@ -4,8 +4,7 @@
// SPDX-FileCopyrightText: 2017 Todd Strader
// SPDX-License-Identifier: CC0-1.0
module t (
);
module t;
localparam the_localparam = 8'd256;

2
test_regress/t/t_lint_misindent_bad.v
View File

@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
// Do not reindent - spaces are critical to this test
// verilog_format: off
// verilator lint_off UNUSEDLOOP
module t;

6
test_regress/t/t_mod_mod.out
View File

@ -1,15 +1,15 @@
%Error-UNSUPPORTED: t/t_mod_mod.v:10:3: Unsupported: module decls within module decls
10 | program p_in_m();
10 | program p_in_m;
| ^~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_mod_mod.v:12:3: Unsupported: program decls within module decls
12 | interface i_in_m();
12 | interface i_in_m;
| ^~~~~~~~~
%Error-UNSUPPORTED: t/t_mod_mod.v:14:1: Unsupported: interface decls within module decls
14 | endmodule
| ^~~~~~~~~
%Error-UNSUPPORTED: t/t_mod_mod.v:19:3: Unsupported: interface decls within interface decls
19 | program p_in_i();
19 | program p_in_i;
| ^~~~~~~
%Error-UNSUPPORTED: t/t_mod_mod.v:21:1: Unsupported: program decls within interface decls
21 | endinterface

12
test_regress/t/t_mod_mod.v
View File

@ -4,18 +4,18 @@
// SPDX-FileCopyrightText: 2008 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module m();
module m;
module m_in_m;
endmodule
program p_in_m();
program p_in_m;
endprogram
interface i_in_m();
interface i_in_m;
endinterface
endmodule
interface i();
interface i_in_i();
interface i;
interface i_in_i;
endinterface
program p_in_i();
program p_in_i;
endprogram
endinterface

2
test_regress/t/t_pp_lib.v
View File

@ -7,5 +7,5 @@
`include "t_pp_lib_inc.vh"
module t;
wire [`WIDTH-1:0] a;
library_cell n1(a);
library_cell n1 (a);
endmodule

6
test_regress/t/t_process_propagation.v
View File

@ -56,10 +56,8 @@ module t;
->evt1;
@evt2 begin
if (!foo.event_received)
$stop;
if (bar.event_received)
$stop;
if (!foo.event_received) $stop;
if (bar.event_received) $stop;
$write("*-* All Finished *-*\n");
$finish;

10
test_regress/t/t_property_arg_type.v
View File

@ -7,17 +7,17 @@
// Test to assert that property argument type is not retained from
// the previous variable and is not causing errors
module t(input clk);
module t (
input clk
);
genvar i;
property prop(prop_arg);
@(posedge clk)
(prop_arg |-> prop_arg);
@(posedge clk) (prop_arg |-> prop_arg);
endproperty
wire w;
property prop2(prop_arg);
@(posedge clk)
(prop_arg |-> prop_arg);
@(posedge clk) (prop_arg |-> prop_arg);
endproperty
initial begin

8
test_regress/t/t_scheduling_2.v
View File

@ -14,8 +14,8 @@
`define IMPURE_ONE |($random | $random);
`endif
module top(
clk
module top (
clk
);
input clk;
@ -41,7 +41,7 @@ module top(
end
always @(clk) a = cyc + `IMPURE_ONE;
always @(a) b = a + `IMPURE_ONE;
assign c = a + `IMPURE_ONE;
always @(a) b = a + `IMPURE_ONE;
assign c = a + `IMPURE_ONE;
endmodule

8
test_regress/t/t_scheduling_3.v
View File

@ -14,8 +14,8 @@
`define IMPURE_ONE |($random | $random);
`endif
module top(
clk
module top (
clk
);
input clk;
@ -40,8 +40,8 @@ module top(
cyc <= cyc + 1;
end
always @(a) b = a + `IMPURE_ONE;
always @(a) b = a + `IMPURE_ONE;
always @(cyc) a = cyc + `IMPURE_ONE;
assign c = a + `IMPURE_ONE;
assign c = a + `IMPURE_ONE;
endmodule

8
test_regress/t/t_scheduling_4.v
View File

@ -14,8 +14,8 @@
`define IMPURE_ONE |($random | $random);
`endif
module top(
clk
module top (
clk
);
input clk;
@ -43,7 +43,7 @@ module top(
end
always @(edge cyc[0]) a = cyc + `IMPURE_ONE;
always @(edge a[0]) b = a + `IMPURE_ONE;
assign c = a + `IMPURE_ONE;
always @(edge a[0]) b = a + `IMPURE_ONE;
assign c = a + `IMPURE_ONE;
endmodule

2
test_regress/t/t_scheduling_5.v
View File

@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
module t (
input clk
input clk
);
reg start = 0;

8
test_regress/t/t_static_dup_name.v
View File

@ -7,17 +7,17 @@ module t;
function void do_stuff();
static int some_int;
begin: block0
begin : block0
static int some_int;
end
begin: block1
begin : block1
static int some_int;
end
begin
static int some_int;
end
begin: block2
begin: block3
begin : block2
begin : block3
static int some_int;
end
begin

6
test_regress/t/t_std_randomize_with.v
View File

@ -10,8 +10,8 @@ class external_cl;
logic [7:0] dyn[][];
function new();
x = 0;
y = 0;
x = 0;
y = 0;
dyn = new[4];
foreach (dyn[i]) dyn[i] = new[1];
endfunction
@ -21,7 +21,7 @@ module t;
initial begin
int a, b;
automatic int limit = 10;
external_cl obj;
external_cl obj;
// Test 1: Basic std::randomize with 'with' clause
if (std::randomize(

4
test_regress/t/t_stream_bad.v
View File

@ -7,8 +7,8 @@
module t;
logic [31:0] packed_data_32;
byte byte_in [4];
logic [ 3:0] x = 4'($random());
byte byte_in[4];
logic [3:0] x = 4'($random());
initial begin
packed_data_32 = {<<$random{byte_in}};

6
test_regress/t/t_struct_array_assignment.v
View File

@ -12,7 +12,7 @@ class unconstrained_struct_array_test;
int field_c;
} simple_struct_t;
simple_struct_t struct_array[3]; // Unpacked array
simple_struct_t struct_array[3]; // Unpacked array
function new();
// Initialize struct_array
@ -31,13 +31,13 @@ class unconstrained_struct_array_test;
endclass
module t_struct_array_assignment;
unconstrained_struct_array_test cl;
unconstrained_struct_array_test cl;
initial begin
cl = new();
foreach(cl.struct_array[i]) begin
foreach (cl.struct_array[i]) begin
cl.struct_array[i].field_a = i;
cl.struct_array[i].field_b = i + 1;
cl.struct_array[i].field_c = i + 2;

2
test_regress/t/t_struct_port.v
View File

@ -11,7 +11,7 @@ typedef struct packed {
} pack_t;
module t (
input clk
input clk
);
integer cyc = 0;

2
test_regress/t/t_timing_class_static_delay.v
View File

@ -23,7 +23,7 @@ module t;
foo.wait_dynamically();
if ($time != `DELAY) $stop;
Foo::wait_statically();
if ($time != 2*`DELAY) $stop;
if ($time != 2 * `DELAY) $stop;
$write("*-* All Finished *-*\n");
$finish;
end

6
test_regress/t/t_timing_dpi_unsup.out
View File

@ -1,5 +1,5 @@
%Error-UNSUPPORTED: t/t_timing_dpi_unsup.v:28:15: Unsupported: Timing controls inside DPI-exported tasks
28 | repeat(n) @(negedge clk);
| ^
%Error-UNSUPPORTED: t/t_timing_dpi_unsup.v:28:16: Unsupported: Timing controls inside DPI-exported tasks
28 | repeat (n) @(negedge clk);
| ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

14
test_regress/t/t_timing_dpi_unsup.v
View File

@ -5,13 +5,13 @@
// SPDX-License-Identifier: CC0-1.0
`ifdef TEST_VERBOSE
`define WRITE_VERBOSE(msg) $write(msg)
`define WRITE_VERBOSE(msg) $write(msg)
`else
`define WRITE_VERBOSE(msg)
`define WRITE_VERBOSE(msg)
`endif
`default_nettype none
`timescale 1ns/1ps
`timescale 1ns / 1ps
module t;
@ -25,7 +25,7 @@ module t;
export "DPI-C" task tb_sv_wait;
task automatic tb_sv_wait(input int n);
`WRITE_VERBOSE("tb_sv_wait start...\n");
repeat(n) @(negedge clk);
repeat (n) @(negedge clk);
`WRITE_VERBOSE("tb_sv_wait done!\n");
endtask
@ -33,14 +33,14 @@ module t;
initial begin
`WRITE_VERBOSE("test start\n");
repeat(10) @(posedge clk);
repeat (10) @(posedge clk);
`WRITE_VERBOSE("calling tb_c_wait...\n");
tb_c_wait();
`WRITE_VERBOSE("tb_c_wait finish\n");
repeat(10) @(posedge clk);
repeat (10) @(posedge clk);
$write("*-* All Finished *-*\n");
$finish;
end
initial #(cycle*30) $stop; // timeout
initial #(cycle * 30) $stop; // timeout
endmodule

12
test_regress/t/t_timing_fork_no_timing_ctrl.v
View File

@ -6,10 +6,10 @@
module t;
initial
fork
begin
$write("*-* All Finished *-*\n");
$finish;
end
join_none
fork
begin
$write("*-* All Finished *-*\n");
$finish;
end
join_none
endmodule

40
test_regress/t/t_timing_func_fork_bad.out
View File

@ -7,40 +7,40 @@
: ... note: In instance 't'
14 | o1 = 0;
| ^~
%Error: t/t_timing_func_fork_bad.v:22:7: Writing to an output automatic variable of a task after a timing control is not allowed (IEEE 1800-2023 13.2.2)
%Error: t/t_timing_func_fork_bad.v:23:9: Writing to an output automatic variable of a task after a timing control is not allowed (IEEE 1800-2023 13.2.2)
: ... note: In instance 't'
22 | o1 = 0;
| ^~
%Error: t/t_timing_func_fork_bad.v:29:9: Writing to an output automatic variable of a function after a timing control is not allowed (IEEE 1800-2023 13.2.2)
: ... note: In instance 't'
29 | f2 = #5 0;
23 | o1 = 0;
| ^~
%Error: t/t_timing_func_fork_bad.v:31:9: Writing to an inout automatic variable of a function after a timing control is not allowed (IEEE 1800-2023 13.2.2)
%Error: t/t_timing_func_fork_bad.v:31:9: Writing to an output automatic variable of a function after a timing control is not allowed (IEEE 1800-2023 13.2.2)
: ... note: In instance 't'
31 | io2 = 0;
31 | f2 = #5 0;
| ^~
%Error: t/t_timing_func_fork_bad.v:33:9: Writing to an inout automatic variable of a function after a timing control is not allowed (IEEE 1800-2023 13.2.2)
: ... note: In instance 't'
33 | io2 = 0;
| ^~~
%Error: t/t_timing_func_fork_bad.v:41:9: Writing to an output automatic variable of a function after a timing control is not allowed (IEEE 1800-2023 13.2.2)
%Error: t/t_timing_func_fork_bad.v:43:9: Writing to an output automatic variable of a function after a timing control is not allowed (IEEE 1800-2023 13.2.2)
: ... note: In instance 't'
41 | f3 = 0;
43 | f3 = 0;
| ^~
%Error: t/t_timing_func_fork_bad.v:42:9: Writing to an output automatic variable of a function after a timing control is not allowed (IEEE 1800-2023 13.2.2)
%Error: t/t_timing_func_fork_bad.v:44:9: Writing to an output automatic variable of a function after a timing control is not allowed (IEEE 1800-2023 13.2.2)
: ... note: In instance 't'
42 | o3 = 0;
44 | o3 = 0;
| ^~
%Error: t/t_timing_func_fork_bad.v:50:9: Writing to an output automatic variable of a function after a timing control is not allowed (IEEE 1800-2023 13.2.2)
%Error: t/t_timing_func_fork_bad.v:52:9: Writing to an output automatic variable of a function after a timing control is not allowed (IEEE 1800-2023 13.2.2)
: ... note: In instance 't'
50 | f4 = @e 0;
52 | f4 = @e 0;
| ^~
%Error: t/t_timing_func_fork_bad.v:52:9: Writing to an inout automatic variable of a function after a timing control is not allowed (IEEE 1800-2023 13.2.2)
%Error: t/t_timing_func_fork_bad.v:54:9: Writing to an inout automatic variable of a function after a timing control is not allowed (IEEE 1800-2023 13.2.2)
: ... note: In instance 't'
52 | io4 = 0;
54 | io4 = 0;
| ^~~
%Error: t/t_timing_func_fork_bad.v:63:9: Writing to an output automatic variable of a function after a timing control is not allowed (IEEE 1800-2023 13.2.2)
%Error: t/t_timing_func_fork_bad.v:65:9: Writing to an output automatic variable of a function after a timing control is not allowed (IEEE 1800-2023 13.2.2)
: ... note: In instance 't'
63 | f5 = 0;
65 | f5 = 0;
| ^~
%Error: t/t_timing_func_fork_bad.v:64:9: Writing to an output automatic variable of a function after a timing control is not allowed (IEEE 1800-2023 13.2.2)
%Error: t/t_timing_func_fork_bad.v:66:9: Writing to an output automatic variable of a function after a timing control is not allowed (IEEE 1800-2023 13.2.2)
: ... note: In instance 't'
64 | o5 = 0;
66 | o5 = 0;
| ^~
%Error: Exiting due to

10
test_regress/t/t_timing_func_fork_bad.v
View File

@ -17,10 +17,12 @@ module t;
endfunction
task automatic t1(output int o1);
fork begin
#1 $stop;
o1 = 0;
end join_none
fork
begin
#1 $stop;
o1 = 0;
end
join_none
endtask
function automatic int f2(inout io2);

18
test_regress/t/t_timing_initial_always.v
View File

@ -6,20 +6,24 @@
module t;
wire sig;
foo foo(sig);
foo foo (sig);
initial #1 begin
$write("*-* All Finished *-*\n");
$finish();
end
initial
#1 begin
$write("*-* All Finished *-*\n");
$finish();
end
endmodule
module foo(inout sig);
module foo (
inout sig
);
reg cond = $c(0);
always @(sig) begin
if (cond) begin
#1; $c("");
#1;
$c("");
end
end
endmodule

6
test_regress/t/t_timing_unset3.out
View File

@ -1,6 +1,6 @@
%Error-NEEDTIMINGOPT: t/t_clocking_notiming.v:11:8: Use --timing or --no-timing to specify how clocking output skew greater than #0 should be handled
%Error-NEEDTIMINGOPT: t/t_clocking_notiming.v:11:5: Use --timing or --no-timing to specify how clocking output skew greater than #0 should be handled
: ... note: In instance 't'
11 | output #1 out;
| ^~~~~~
11 | output #1 out;
| ^~~~~~
... For error description see https://verilator.org/warn/NEEDTIMINGOPT?v=latest
%Error: Exiting due to

4
test_regress/t/t_timing_zerodly.v
View File

@ -29,11 +29,11 @@ class Foo;
my_bit = 1;
end : finish_before
join_none
#1 $display("After fork."); // Check if there's no skipped coroutine
#1 $display("After fork."); // Check if there's no skipped coroutine
endtask
endclass
module test();
module test;
initial begin
Foo::fork_w_zerodly($time);
$write("*-* All Finished *-*\n");

58
test_regress/t/t_to_string_emitted.v
View File

@ -100,8 +100,8 @@ endclass
module t;
struct_t s;
iface i1();
iface2 i2();
iface i1 ();
iface2 i2 ();
Class c;
Derived d;
Derived2 d2;
@ -113,38 +113,38 @@ module t;
OuterClass::NestedClass nc;
Class3 c3;
Class4 c4;
iface3 i3();
iface3 i3 ();
initial begin
c = new;
c.i1 = i1;
c.i2[0][0] = i2;
d = new;
d2 = new;
d2.c2 = new;
b2 = d2;
d3 = new;
iclass = d3;
d4 = new;
iclass2 = d4;
nc = new;
c3 = new;
c3.i = i3;
c4 = new;
c4.i = i3;
c = new;
c.i1 = i1;
c.i2[0][0] = i2;
d = new;
d2 = new;
d2.c2 = new;
b2 = d2;
d3 = new;
iclass = d3;
d4 = new;
iclass2 = d4;
nc = new;
c3 = new;
c3.i = i3;
c4 = new;
c4.i = i3;
`ifdef DISPLAY_OBJECTS
$display("struct: '%p'", s);
$display("class: '%p'", c);
$display("class from subclass: '%p'", d);
$display("class from superclass: '%p'", b2);
$display("class from interface: '%p'", iclass);
$display("class from interface 2: '%p'", d4);
$display("nested class: '%p'", nc);
$display("classes with shared field types: '%p', '%p'", c3, c4);
$display("struct: '%p'", s);
$display("class: '%p'", c);
$display("class from subclass: '%p'", d);
$display("class from superclass: '%p'", b2);
$display("class from interface: '%p'", iclass);
$display("class from interface 2: '%p'", d4);
$display("nested class: '%p'", nc);
$display("classes with shared field types: '%p', '%p'", c3, c4);
`endif
$write("*-* All Finished *-*\n");
$finish;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

8
test_regress/t/t_to_string_emitted_class_hierarchy.v
View File

@ -66,12 +66,12 @@ module t;
`endif
initial begin
$display("'%p'", printed_obj);
$display("'%p'", printed_obj);
`ifdef OBJ_TYPE2
$display("'%p'", printed_obj2);
$display("'%p'", printed_obj2);
`endif
$write("*-* All Finished *-*\n");
$finish;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_trace_lib_as_top.v
View File

@ -5,15 +5,15 @@
`define STRINGIFY(x) `"x`"
module t(
input clk
module t (
input clk
);
int cyc = 1;
Factorial factorial(
.clk(clk),
.i(cyc)
Factorial factorial (
.clk(clk),
.i(cyc)
);
initial begin
@ -22,16 +22,16 @@ module t(
end
always @(posedge clk) begin
cyc <= cyc+1;
cyc <= cyc + 1;
if (cyc == 5) begin
$finish;
end
end
endmodule
module Factorial(
input clk,
input int i
module Factorial (
input clk,
input int i
);
int fact = 1;
always @(posedge clk) begin

6
test_regress/t/t_typedef_id_bad.out
View File

@ -1,5 +1,5 @@
%Error: t/t_typedef_id_bad.v:9:34: Expecting a data type, not VARREF: 'i'
9 | class Cls #(parameter type P_T = i);
| ^
%Error: t/t_typedef_id_bad.v:10:26: Expecting a data type, not VARREF: 'i'
10 | parameter type P_T = i
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

4
test_regress/t/t_typedef_id_bad.v
View File

@ -6,5 +6,7 @@
int i;
class Cls #(parameter type P_T = i);
class Cls #(
parameter type P_T = i
);
endclass

6
test_regress/t/t_uvm_typeof_type.v
View File

@ -43,13 +43,13 @@ class uvm_reg_item extends uvm_sequence_item;
endclass
virtual class uvm_sequence #(
type REQ = uvm_sequence_item,
type RSP = REQ
type REQ = uvm_sequence_item,
type RSP = REQ
) extends uvm_object;
endclass
class uvm_reg_sequence #(
type BASE = uvm_sequence#(uvm_reg_item)
type BASE = uvm_sequence#(uvm_reg_item)
) extends BASE;
function new;
factory.register(this, "uvm_reg_sequence");

3
test_regress/t/t_var_extern_method_lifetime.v
View File

@ -27,8 +27,7 @@ module t;
foo2 = new(2);
foo1.add_in_fork_delayed(10, foo2);
#20;
if (foo1.m_v != 3)
$stop;
if (foo1.m_v != 3) $stop;
$write("*-* All Finished *-*\n");
$finish;
end

21
test_regress/t/t_var_in_fork.v
View File

@ -20,14 +20,12 @@ module t;
int my_var;
int my_other_var;
my_var = captured_var;
my_other_var = captured_var; /* Capture the same value "twice" */
my_other_var = captured_var; /* Capture the same value "twice" */
my_var++;
static_var++; /* Write to a value with static lifetime (valid) */
static_var++; /* Write to a value with static lifetime (valid) */
$display("Vars in forked process: %0d %0d", my_var, my_other_var);
if (my_var != 2)
$stop;
if (my_other_var != 1)
$stop;
if (my_var != 2) $stop;
if (my_other_var != 1) $stop;
send_event();
end
join_none
@ -45,14 +43,13 @@ module t;
always @(evt) begin
$display("Static variable: %0d", static_var);
if (static_var != 1)
$stop;
if (static_var != 1) $stop;
fork
begin
automatic int my_auto_var = 0;
my_auto_var++;
$display("Automatic variable in fork: %0d", my_auto_var);
if (my_auto_var != 1) $stop;
automatic int my_auto_var = 0;
my_auto_var++;
$display("Automatic variable in fork: %0d", my_auto_var);
if (my_auto_var != 1) $stop;
end
join_none
$write("*-* All Finished *-*\n");

2
test_regress/t/t_verilated_all.v
View File

@ -27,7 +27,7 @@ module t (
c = new;
rand_result = c.randomize();
$display("rand: %x x: %x ", rand_result, c.x); // Get verilated_random.cpp
force frc=42; // Get verilated_force.h
force frc = 42; // Get verilated_force.h
$write("*-* All Finished *-*\n");
$finish;
end

24
test_regress/t/t_virtual_interface_method_bad.v
View File

@ -9,27 +9,27 @@ class ExampleClass;
task run();
v_if.x();
endtask: run
endtask : run
function void bind_if(virtual example_if v_if);
this.v_if = v_if;
endfunction: bind_if
endclass: ExampleClass
endfunction : bind_if
endclass : ExampleClass
interface example_if();
logic clk;
logic rstn;
logic[7:0] x;
endinterface: example_if
interface example_if ();
logic clk;
logic rstn;
logic [7:0] x;
endinterface : example_if
module t;
example_if example_if_inst();
example_if example_if_inst ();
initial begin: main
initial begin : main
automatic ExampleClass exampleClass = new();
exampleClass.bind_if(example_if_inst);
exampleClass.run();
end: main
endmodule: t
end : main
endmodule : t