42 lines
991 B
Systemverilog
42 lines
991 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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wire a;
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assign (weak0, weak1) a = 1;
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assign (weak0, supply1) a = 1;
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assign (strong0, strong1) a = 0;
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wire (weak0, weak1) b = 1;
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assign (strong0, strong1) b = 0;
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wire [1:0] c;
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assign (weak0, supply1) c = 2'b11;
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assign (supply0, pull1) c = 2'b11;
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assign (strong0, strong1) c = 0;
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wire [1:0] cr;
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assign (supply1, weak0) cr = 2'b11;
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assign (pull1, supply0) cr = 2'b11;
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assign (strong1, strong0) cr = 0;
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supply0 d;
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assign (strong0, strong1) d = 1;
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wire (supply0, supply1) e = 1'bz;
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assign (weak0, weak1) e = 1;
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always begin
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if (a !== 1'b1) $stop;
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if (b !== 1'b0) $stop;
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if (c !== 2'b11) $stop;
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if (cr !== 2'b11) $stop;
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if (e !== 1'b1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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