verilator/test_regress
Krzysztof Bieganski 0eaa9ed144
Fix `--timing` with `--x-initial-edge` (#6603) (#6631)
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2025-11-03 09:39:23 -05:00
..
t Fix `--timing` with `--x-initial-edge` (#6603) (#6631) 2025-11-03 09:39:23 -05:00
.gdbinit
.gitignore
CMakeLists.txt
Makefile Internals: Run format-make 2025-11-01 14:12:47 -04:00
Makefile_obj
driver.py Internals: Add more python strict typing. No functional change intended 2025-11-01 14:14:56 -04:00
input.vc
input.xsim.vc