35 lines
581 B
Systemverilog
35 lines
581 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int i_header;
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int i_len;
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byte i_data[];
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int i_crc;
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int o_header;
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int o_len;
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byte o_data[];
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int o_crc;
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initial begin
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byte pkt[$];
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i_header = 12;
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i_len = 5;
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i_data = new[5];
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i_crc = 42;
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pkt = {<<8{i_header, i_len, i_data, i_crc}};
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{<<8{o_header, o_len, o_data, o_crc}} = pkt;
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$finish;
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end
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endmodule
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