33 lines
766 B
Systemverilog
33 lines
766 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input logic a2_i,
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a1_i,
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a0_i,
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input logic b_i,
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output logic d_o
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);
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// verilator lint_off PINMISSING
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Sub sub (.a_i({a2_i, a1_i, a0_i}), .b_i, .d_o);
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// verilator lint_on PINMISSING
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endmodule
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module Sub (
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input logic [2:0] a_i,
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input logic b_i,
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output logic c_o,
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output logic d_o
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);
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assign c_o = (a_i != 0) ? 1 : 0;
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assign d_o = // Note = not == below
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(
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c_o = 1 // <--- Warning: ASSIGNEQEXPR
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) ? 1 : (
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c_o = 0 // <--- Warning: ASSIGNEQEXPR
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) ? b_i : 0;
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endmodule
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