Version bump

Signed-off-by: Wilson Snyder <[email protected]>

Changes

@@ -3,6 +3,42 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in []. Thanks!
 
 
+* Verilator 3.906 2017-06-22
+
+***   Support set_time_unit/set_time_precision in C traces, msg2261.
+
+***   Fix extract of packed array with non-zero LSB, bug1172. [James Pallister]
+
+***   Fix shifts by more than 32-bit numbers, bug1174. [Clifford Wolf]
+
+***   Fix power operator on wide constants, bug761. [Clifford Wolf]
+
+***   Fix .* on interface pins, bug1176. [Maciej Piechotka]
+
+
+* Verilator 3.904 2017-05-30
+
+***   Fix non-cutable ordering loops on clock arrays, bug1009. [Todd Strader]
+
+***   Support ports of array of reals, bug1154. [J Briquet]
+
+***   Support arrayed parameter overrides, bug1153. [John Stevenson]
+
+***   Support $value$plusargs with variables, bug1165. [Wesley Terpstra]
+
+****  Support modport access to un-modport objects, bug1161. [Todd Strader]
+
+****  Add stack trace when can't optimize function, bug1158. [Todd Strader]
+
+****  Add warning on mis-sized literal, bug1156. [Todd Strader]
+
+****  Fix interface functions returning wrong parameters, bug996. [Todd Strader]
+
+****  Fix non-arrayed cells with interface arrays, bug1153. [John Stevenson]
+
+****  Fix --assert with complex case statements, bug1164. [Enzo Chi]
+
+
 * Verilator 3.902 2017-04-02
 
 **    Add -FI option to force includes,msg2146. [Amir Gonnen]

bin/verilator

@@ -495,6 +495,10 @@ If the signal is the input to top-module, the directly the signal name. If you
 find it difficult to find the exact name, try to use C</*verilator clocker*/> in
 RTL file to mark the signal directly.
 
+If clock signals are assigned to vectors and then later used individually,
+Verilator will attempt to decompose the vector and connect the single-bit
+clock signals directly.  This should be transparent to the user.
+
 =item --compiler I<compiler-name>
 
 Enables tunings and workarounds for the specified C++ compiler.
@@ -1913,54 +1917,71 @@ documented below.
 Verilator has an important difference from an event based simulator; signal
 values that are changed by the VPI will not immediately propagate their
 values, instead the top level header file's eval() method must be called.
-Normally this would be part of the normal evaluation (IE the next clock
+Normally this would be part of the normal evaluation (i.e. the next clock
 edge), not as part of the value change.  This makes the performance of VPI
 routines extremely fast compared to event based simulators, but can confuse
 some test-benches that expect immediate propagation.
 
-Note the VPI by it's specified implementation will always be much slower
+Note the VPI by its specified implementation will always be much slower
 than accessing the Verilator values by direct reference
 (structure->module->signame), as the VPI accessors perform lookup in
 functions at runtime requiring at best hundreds of instructions, while the
 direct references are evaluated by the compiler and result in only a couple
 of instructions.
 
+For signal callbacks to work the main loop of the program must call
+VerilatedVpi::callValueCbs().
+
 =head2 VPI Example
 
 In the below example, we have readme marked read-only, and writeme which if
 written from outside the model will have the same semantics as if it
 changed on the specified clock edge.
 
-    module t;
-       reg readme   /*verilator public_flat_rd*/;
-       reg writeme  /*verilator public_flat_rw @(posedge clk) */;
-    endmodule
+    cat <<EOF >our.v
+      module our (input clk);
+         reg readme   /*verilator public_flat_rd*/;
+         reg writeme  /*verilator public_flat_rw @(posedge clk) */;
+         initial $finish;
+      endmodule
+    EOF
 
 There are many online tutorials and books on the VPI, but an example that
-accesses the above would be:
+accesses the above signal "readme" would be:
 
-    void read_and_check() {
-        vpiHandle vh1 = vpi_handle_by_name((PLI_BYTE8*)"t.readme", NULL);
-        if (!vh1) { error... }
-        const char* name = vpi_get_str(vpiName, vh1);
-        printf("Module name: %s\n");  // Prints "readme"
+    cat <<EOF >sim_main.cpp
+      #include "Vour.h"
+      #include "verilated.h"
+      #include "verilated_vpi.h"  // Required to get definitions
 
-        s_vpi_value v;
-        v.format = vpiIntVal;
-        vpi_get_value(vh1, &v);
-        printf("Value of v: %d\n", v.value.integer);  // Prints "readme"
-    }
+      vluint64_t main_time = 0;   // See comments in first example
+      double sc_time_stamp () { return main_time; }
 
-For signal callbacks to work the main loop of the program must call
-VerilatedVpi::callValueCbs().
+      void read_and_check() {
+          vpiHandle vh1 = vpi_handle_by_name((PLI_BYTE8*)"TOP.our.readme", NULL);
+          if (!vh1) { vl_fatal(__FILE__, __LINE__, "sim_main", "No handle found"); }
+          const char* name = vpi_get_str(vpiName, vh1);
+          printf("Module name: %s\n", name);  // Prints "readme"
 
-    #include "verilated_vpi.h"  // Required to get definitions
-    ...
-    while (time passes) {
-        ...
-        topp->eval();
-        VerilatedVpi::callValueCbs();
-    }
+          s_vpi_value v;
+          v.format = vpiIntVal;
+          vpi_get_value(vh1, &v);
+          printf("Value of v: %d\n", v.value.integer);  // Prints "readme"
+      }
+
+      int main(int argc, char **argv, char **env) {
+          Verilated::commandArgs(argc, argv);
+          Vour* top = new Vour;
+          Verilated::internalsDump();  // See scopes to help debug
+          while (!Verilated::gotFinish()) {
+              top->eval();
+              VerilatedVpi::callValueCbs();  // For signal callbacks
+              read_and_check();
+          }
+          delete top;
+          exit(0);
+      }
+    EOF
 
 
 =head1 CROSS COMPILATION

configure.ac

@@ -6,7 +6,7 @@
 
 #AC_INIT([Verilator],[#.### YYYY-MM-DD])
 #AC_INIT([Verilator],[#.### devel])
-AC_INIT([Verilator],[3.902 2017-04-02])
+AC_INIT([Verilator],[3.906 2017-06-22])
 # When releasing, also update header of Changes file
 
 AC_CONFIG_HEADER(src/config_build.h)

include/verilated.cpp

@@ -115,7 +115,7 @@ QData VL_RANDOM_Q(int obits) {
 }
 
 WDataOutP VL_RANDOM_W(int obits, WDataOutP outwp) {
-    for (int i=0; i<VL_WORDS_I(obits); i++) {
+    for (int i=0; i<VL_WORDS_I(obits); ++i) {
 	if (i<(VL_WORDS_I(obits)-1)) {
 	    outwp[i] = VL_RAND32();
 	} else {
@@ -146,7 +146,7 @@ QData VL_RAND_RESET_Q(int obits) {
 }
 
 WDataOutP VL_RAND_RESET_W(int obits, WDataOutP outwp) {
-    for (int i=0; i<VL_WORDS_I(obits); i++) {
+    for (int i=0; i<VL_WORDS_I(obits); ++i) {
 	if (i<(VL_WORDS_I(obits)-1)) {
 	    outwp[i] = VL_RAND_RESET_I(32);
 	} else {
@@ -157,7 +157,7 @@ WDataOutP VL_RAND_RESET_W(int obits, WDataOutP outwp) {
 }
 
 WDataOutP VL_ZERO_RESET_W(int obits, WDataOutP outwp) {
-    for (int i=0; i<VL_WORDS_I(obits); i++) outwp[i] = 0;
+    for (int i=0; i<VL_WORDS_I(obits); ++i) outwp[i] = 0;
     return outwp;
 }
 
@@ -166,7 +166,7 @@ WDataOutP VL_ZERO_RESET_W(int obits, WDataOutP outwp) {
 
 void _VL_DEBUG_PRINT_W(int lbits, WDataInP iwp) {
     VL_PRINTF("  Data: w%d: ", lbits);
-    for (int i=VL_WORDS_I(lbits)-1; i>=0; i--) { VL_PRINTF("%08x ",iwp[i]); }
+    for (int i=VL_WORDS_I(lbits)-1; i>=0; --i) { VL_PRINTF("%08x ",iwp[i]); }
     VL_PRINTF("\n");
 }
 
@@ -179,7 +179,7 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, boo
     // for debug see V3Number version
     // Requires clean input
     int words = VL_WORDS_I(lbits);
-    for (int i=0; i<words; i++) owp[i]=0;
+    for (int i=0; i<words; ++i) owp[i]=0;
     // Find MSB and check for zero.
     int umsbp1 = VL_MOSTSETBITP1_W(words,lwp); // dividend
     int vmsbp1 = VL_MOSTSETBITP1_W(words,rwp); // divisor
@@ -193,14 +193,14 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, boo
 
     if (vw == 1) {  // Single divisor word breaks rest of algorithm
 	vluint64_t k = 0;
-	for (int j = uw-1; j >= 0; j--) {
+	for (int j = uw-1; j >= 0; --j) {
 	    vluint64_t unw64 = ((k<<VL_ULL(32)) + (vluint64_t)(lwp[j]));
 	    owp[j] = unw64 / (vluint64_t)(rwp[0]);
 	    k      = unw64 - (vluint64_t)(owp[j])*(vluint64_t)(rwp[0]);
 	}
 	if (is_modulus) {
 	    owp[0] = k;
-	    for (int i=1; i<words; i++) owp[i]=0;
+	    for (int i=1; i<words; ++i) owp[i]=0;
 	}
 	return owp;
     }
@@ -211,13 +211,13 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, boo
 
     // Zero for ease of debugging and to save having to zero for shifts
     // Note +1 as loop will use extra word
-    for (int i=0; i<words+1; i++) { un[i]=vn[i]=0; }
+    for (int i=0; i<words+1; ++i) { un[i]=vn[i]=0; }
 
     // Algorithm requires divisor MSB to be set
     // Copy and shift to normalize divisor so MSB of vn[vw-1] is set
     int s = 31-VL_BITBIT_I(vmsbp1-1);  // shift amount (0...31)
     vluint32_t shift_mask = s ? 0xffffffff : 0;  // otherwise >> 32 won't mask the value
-    for (int i = vw-1; i>0; i--) {
+    for (int i = vw-1; i>0; --i) {
 	vn[i] = (rwp[i] << s) | (shift_mask & (rwp[i-1] >> (32-s)));
     }
     vn[0] = rwp[0] << s;
@@ -225,13 +225,13 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, boo
     // Copy and shift dividend by same amount; may set new upper word
     if (s) un[uw] = lwp[uw-1] >> (32-s);
     else un[uw] = 0;
-    for (int i=uw-1; i>0; i--) {
+    for (int i=uw-1; i>0; --i) {
 	un[i] = (lwp[i] << s) | (shift_mask & (lwp[i-1] >> (32-s)));
     }
     un[0] = lwp[0] << s;
 
     // Main loop
-    for (int j = uw - vw; j >= 0; j--) {
+    for (int j = uw - vw; j >= 0; --j) {
 	// Estimate
 	vluint64_t unw64 = ((vluint64_t)(un[j+vw])<<VL_ULL(32) | (vluint64_t)(un[j+vw-1]));
 	vluint64_t qhat = unw64 / (vluint64_t)(vn[vw-1]);
@@ -247,7 +247,7 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, boo
 
 	vlsint64_t t = 0;  // Must be signed
 	vluint64_t k = 0;
-	for (int i=0; i<vw; i++) {
+	for (int i=0; i<vw; ++i) {
 	    vluint64_t p = qhat*vn[i];  // Multiply by estimate
 	    t = un[i+j] - k - (p & VL_ULL(0xFFFFFFFF));  // Subtract
 	    un[i+j] = t;
@@ -261,7 +261,7 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, boo
 	    // Over subtracted; correct by adding back
 	    owp[j]--;
 	    k = 0;
-	    for (int i=0; i<vw; i++) {
+	    for (int i=0; i<vw; ++i) {
 		t = (vluint64_t)(un[i+j]) + (vluint64_t)(vn[i]) + k;
 		un[i+j] = t;
 		k = t >> VL_ULL(32);
@@ -272,16 +272,58 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, boo
 
     if (is_modulus) { // modulus
 	// Need to reverse normalization on copy to output
-	for (int i=0; i<vw; i++) {
+	for (int i=0; i<vw; ++i) {
 	    owp[i] = (un[i] >> s) | (shift_mask & (un[i+1] << (32-s)));
 	}
-	for (int i=vw; i<words; i++) owp[i] = 0;
+	for (int i=vw; i<words; ++i) owp[i] = 0;
 	return owp;
     } else { // division
 	return owp;
     }
 }
 
+WDataOutP VL_POW_WWW(int obits, int, int rbits, WDataOutP owp, WDataInP lwp, WDataInP rwp) {
+    owp[0] = 1;
+    for (int i=1; i < VL_WORDS_I(obits); i++) owp[i] = 0;
+    // cppcheck-suppress variableScope
+    WData powstore[VL_MULS_MAX_WORDS]; // Fixed size, as MSVC++ doesn't allow [words] here
+    WData lastpowstore[VL_MULS_MAX_WORDS]; // Fixed size, as MSVC++ doesn't allow [words] here
+    WData lastoutstore[VL_MULS_MAX_WORDS]; // Fixed size, as MSVC++ doesn't allow [words] here
+    // cppcheck-suppress variableScope
+    VL_ASSIGN_W(obits, powstore, lwp);
+    for (int bit=0; bit<rbits; bit++) {
+	if (bit>0) {  // power = power*power
+	    VL_ASSIGN_W(obits, lastpowstore, powstore);
+	    VL_MUL_W(VL_WORDS_I(obits), powstore, lastpowstore, lastpowstore);
+	}
+	if (VL_BITISSET_W(rwp,bit)) {  // out *= power
+	    VL_ASSIGN_W(obits, lastoutstore, owp);
+	    VL_MUL_W(VL_WORDS_I(obits), owp, lastoutstore, powstore);
+	}
+    }
+    return owp;
+}
+
+WDataOutP VL_POWSS_WWW(int obits, int, int rbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, bool lsign, bool rsign) {
+    if (rsign && VL_SIGN_W(rbits, rwp)) {
+	int words = VL_WORDS_I(obits);
+	VL_ZERO_W(obits, owp);
+	IData lor = 0; // 0=all zeros, ~0=all ones, else mix
+	for (int i=1; i < (words-1); ++i) {
+	    lor |= lwp[i];
+	}
+	lor |= ( (lwp[words-1] == VL_MASK_I(rbits)) ? ~VL_UL(0) : 0);
+	if (lor==0 && lwp[0]==0) { return owp; } // "X" so return 0
+	else if (lor==0 && lwp[0]==1) { owp[0] = 1; return owp; } // 1
+	else if (lsign && lor == ~VL_UL(0) && lwp[0]==~VL_UL(0)) {  // -1
+	    if (rwp[0] & 1) { return VL_ALLONES_W(obits, owp); } // -1^odd=-1
+	    else { owp[0] = 1; return owp; } // -1^even=1
+	}
+	return 0;
+    }
+    return VL_POW_WWW(obits, rbits, rbits, owp, lwp, rwp);
+}
+
 //===========================================================================
 // Formatting
 
@@ -302,8 +344,7 @@ void _vl_vsformat(string& output, const char* formatp, va_list ap) {
     bool inPct = false;
     bool widthSet = false;
     int width = 0;
-    const char* pos = formatp;
-    for (; *pos; ++pos) {
+    for (const char* pos = formatp; *pos; ++pos) {
 	if (!inPct && pos[0]=='%') {
 	    pctp = pos;
 	    inPct = true;
@@ -377,7 +418,7 @@ void _vl_vsformat(string& output, const char* formatp, va_list ap) {
 		    if (fmt == 'd' || fmt == '#') fmt = 'x';  // Not supported, but show something
 		}
 		int lsb=lbits-1;
-		if (widthSet && width==0) while (lsb && !VL_BITISSET_W(lwp,lsb)) lsb--;
+		if (widthSet && width==0) while (lsb && !VL_BITISSET_W(lwp,lsb)) --lsb;
 		switch (fmt) {
 		case 'c': {
 		    IData charval = ld & 0xff;
@@ -385,7 +426,7 @@ void _vl_vsformat(string& output, const char* formatp, va_list ap) {
 		    break;
 		}
 		case 's':
-		    for (; lsb>=0; lsb--) {
+		    for (; lsb>=0; --lsb) {
 			lsb = (lsb / 8) * 8; // Next digit
 			IData charval = (lwp[VL_BITWORD_I(lsb)]>>VL_BITBIT_I(lsb)) & 0xff;
 			output += (charval==0)?' ':charval;
@@ -434,13 +475,13 @@ void _vl_vsformat(string& output, const char* formatp, va_list ap) {
 		    break;
 		}
 		case 'b':
-		    for (; lsb>=0; lsb--) {
+		    for (; lsb>=0; --lsb) {
 			output += ((lwp[VL_BITWORD_I(lsb)]>>VL_BITBIT_I(lsb)) & 1) + '0';
 		    }
 		    break;
 		    break;
 		case 'o':
-		    for (; lsb>=0; lsb--) {
+		    for (; lsb>=0; --lsb) {
 			lsb = (lsb / 3) * 3; // Next digit
 			// Octal numbers may span more than one wide word,
 			// so we need to grab each bit separately and check for overrun
@@ -453,7 +494,7 @@ void _vl_vsformat(string& output, const char* formatp, va_list ap) {
 		    break;
 		case 'u':  // Packed 2-state
 		    output.reserve(output.size() + 4*VL_WORDS_I(lbits));
-		    for (int i=0; i<VL_WORDS_I(lbits); i++) {
+		    for (int i=0; i<VL_WORDS_I(lbits); ++i) {
 			output += (char)((lwp[i] >> 0) & 0xff);
 			output += (char)((lwp[i] >> 8) & 0xff);
 			output += (char)((lwp[i] >> 16) & 0xff);
@@ -461,7 +502,7 @@ void _vl_vsformat(string& output, const char* formatp, va_list ap) {
 		    }
 		case 'z':  // Packed 4-state
 		    output.reserve(output.size() + 8*VL_WORDS_I(lbits));
-		    for (int i=0; i<VL_WORDS_I(lbits); i++) {
+		    for (int i=0; i<VL_WORDS_I(lbits); ++i) {
 			output += (char)((lwp[i] >> 0) & 0xff);
 			output += (char)((lwp[i] >> 8) & 0xff);
 			output += (char)((lwp[i] >> 16) & 0xff);
@@ -469,12 +510,12 @@ void _vl_vsformat(string& output, const char* formatp, va_list ap) {
 			output += "\0\0\0\0"; // No tristate
 		    }
 		case 'v': // Strength; assume always strong
-		    for (lsb=lbits-1; lsb>=0; lsb--) {
+		    for (lsb=lbits-1; lsb>=0; --lsb) {
 			if ((lwp[VL_BITWORD_I(lsb)]>>VL_BITBIT_I(lsb)) & 1) output += "St1 ";
 			else output += "St0 ";
 		    }
 		case 'x':
-		    for (; lsb>=0; lsb--) {
+		    for (; lsb>=0; --lsb) {
 			lsb = (lsb / 4) * 4; // Next digit
 			IData charval = (lwp[VL_BITWORD_I(lsb)]>>VL_BITBIT_I(lsb)) & 0xf;
 			output += "0123456789abcdef"[charval];
@@ -547,7 +588,7 @@ static inline void _vl_vsss_setbit(WDataOutP owp, int obits, int lsb, int nbits,
 static inline void _vl_vsss_based(WDataOutP owp, int obits, int baseLog2, const char* strp, int posstart, int posend) {
     // Read in base "2^^baseLog2" digits from strp[posstart..posend-1] into owp of size obits.
     int lsb = 0;
-    for (int i=0, pos=posend-1; i<obits && pos>=posstart; pos--) {
+    for (int i=0, pos=posend-1; i<obits && pos>=posstart; --pos) {
 	switch (tolower (strp[pos])) {
 	case 'x': case 'z': case '?': //FALLTHRU
 	case '0': lsb += baseLog2; break;
@@ -615,7 +656,7 @@ IData _vl_vsscanf(FILE* fp,  // If a fscanf
 		if (obits > VL_QUADSIZE) {
 		    owp = va_arg(ap,WDataOutP);
 		}
-		for (int i=0; i<VL_WORDS_I(obits); i++) owp[i] = 0;
+		for (int i=0; i<VL_WORDS_I(obits); ++i) owp[i] = 0;
 		switch (fmt) {
 		case 'c': {
 		    int c = _vl_vsss_peek(fp,floc,fromp,fstr);
@@ -630,7 +671,7 @@ IData _vl_vsscanf(FILE* fp,  // If a fscanf
 		    if (!tmp[0]) goto done;
 		    int pos = ((int)strlen(tmp))-1;
 		    int lsb = 0;
-		    for (int i=0; i<obits && pos>=0; pos--) {
+		    for (int i=0; i<obits && pos>=0; --pos) {
 			_vl_vsss_setbit(owp,obits,lsb, 8, tmp[pos]); lsb+=8;
 		    }
 		    break;
@@ -724,7 +765,7 @@ void _VL_VINT_TO_STRING(int obits, char* destoutp, WDataInP sourcep) {
     int lsb=obits-1;
     bool start=true;
     char* destp = destoutp;
-    for (; lsb>=0; lsb--) {
+    for (; lsb>=0; --lsb) {
 	lsb = (lsb / 8) * 8; // Next digit
 	IData charval = (sourcep[VL_BITWORD_I(lsb)]>>VL_BITBIT_I(lsb)) & 0xff;
 	if (!start || charval) {
@@ -742,8 +783,8 @@ void _VL_STRING_TO_VINT(int obits, void* destp, int srclen, const char* srcp) {
     char* op = ((char*)(destp));
     if (srclen > bytes) srclen = bytes;  // Don't overflow destination
     int i;
-    for (i=0; i<srclen; i++) { *op++ = srcp[srclen-1-i]; }
-    for (; i<bytes; i++) { *op++ = 0; }
+    for (i=0; i<srclen; ++i) { *op++ = srcp[srclen-1-i]; }
+    for (; i<bytes; ++i) { *op++ = 0; }
 }
 
 IData VL_FGETS_IXI(int obits, void* destp, IData fpi) {
@@ -780,7 +821,7 @@ IData VL_FOPEN_NI(const string& filename, IData mode) {
     return VL_FOPEN_S(filename.c_str(), modez);
 }
 IData VL_FOPEN_QI(QData filename, IData mode) {
-    IData fnw[2];  VL_SET_WQ(fnw, filename);
+    WData fnw[2];  VL_SET_WQ(fnw, filename);
     return VL_FOPEN_WI(2, fnw, mode);
 }
 IData VL_FOPEN_WI(int fnwords, WDataInP filenamep, IData mode) {
@@ -914,7 +955,7 @@ IData VL_FSCANF_IX(IData fpi, const char* formatp, ...) {
 }
 
 IData VL_SSCANF_IIX(int lbits, IData ld, const char* formatp, ...) {
-    IData fnw[2];  VL_SET_WI(fnw, ld);
+    WData fnw[2];  VL_SET_WI(fnw, ld);
 
     va_list ap;
     va_start(ap,formatp);
@@ -923,7 +964,7 @@ IData VL_SSCANF_IIX(int lbits, IData ld, const char* formatp, ...) {
     return got;
 }
 IData VL_SSCANF_IQX(int lbits, QData ld, const char* formatp, ...) {
-    IData fnw[2];  VL_SET_WQ(fnw, ld);
+    WData fnw[2];  VL_SET_WQ(fnw, ld);
 
     va_list ap;
     va_start(ap,formatp);
@@ -948,7 +989,7 @@ IData VL_SSCANF_INX(int, const string& ld, const char* formatp, ...) {
 
 void VL_READMEM_Q(bool hex, int width, int depth, int array_lsb, int,
 		  QData ofilename, void* memp, IData start, IData end) {
-    IData fnw[2];  VL_SET_WQ(fnw, ofilename);
+    WData fnw[2];  VL_SET_WQ(fnw, ofilename);
     return VL_READMEM_W(hex,width,depth,array_lsb,2, fnw,memp,start,end);
 }
 
@@ -1061,7 +1102,7 @@ void VL_READMEM_N(bool hex, int width, int depth, int array_lsb, int fnwords,
 }
 
 IData VL_SYSTEM_IQ(QData lhs) {
-    IData lhsw[2];  VL_SET_WQ(lhsw, lhs);
+    WData lhsw[2];  VL_SET_WQ(lhsw, lhs);
     return VL_SYSTEM_IW(2, lhsw);
 }
 IData VL_SYSTEM_IW(int lhswords, WDataInP filenamep) {
@@ -1077,22 +1118,36 @@ IData VL_TESTPLUSARGS_I(const char* formatp) {
     else return 1;
 }
 
-IData VL_VALUEPLUSARGS_IN(int, const char* prefixp, char, string& ldr) {
-    const string& match = VerilatedImp::argPlusMatch(prefixp);
-    const char* dp = match.c_str() + 1 /*leading + */ + strlen(prefixp);
-    if (match == "") return 0;
-    ldr = string(dp);
-    return 1;
-}
+IData VL_VALUEPLUSARGS_INW(int rbits, const string& ld, WDataOutP rwp) {
+    string prefix;
+    bool inPct = false;
+    bool done = false;
+    char fmt = ' ';
+    for (const char* posp = ld.c_str(); !done && *posp; ++posp) {
+	if (!inPct && posp[0]=='%') {
+	    inPct = true;
+	} else if (!inPct) {   // Normal text
+	    prefix += *posp;
+	} else { // Format character
+	    switch (tolower(*posp)) {
+	    case '%':
+		prefix += *posp;
+		inPct = false;
+		break;
+	    default:
+		fmt = *posp;
+		done = true;
+		break;
+	    }
+	}
+    }
 
-IData VL_VALUEPLUSARGS_IW(int rbits, const char* prefixp, char fmt, WDataOutP rwp) {
-    const string& match = VerilatedImp::argPlusMatch(prefixp);
-    const char* dp = match.c_str() + 1 /*leading + */ + strlen(prefixp);
+    const string& match = VerilatedImp::argPlusMatch(prefix.c_str());
+    const char* dp = match.c_str() + 1 /*leading + */ + prefix.length();
     if (match == "") return 0;
+
     VL_ZERO_RESET_W(rbits, rwp);
     switch (tolower(fmt)) {
-    case '%':
-	break;
     case 'd':
 	vlsint64_t ld;
 	sscanf(dp,"%30" VL_PRI64 "d",&ld);
@@ -1108,18 +1163,47 @@ IData VL_VALUEPLUSARGS_IW(int rbits, const char* prefixp, char fmt, WDataOutP rw
     case 'x':
 	_vl_vsss_based(rwp,rbits, 4, dp, 0, (int)strlen(dp));
 	break;
-    case 's':
-	for (int i=0, lsb=0, pos=((int)strlen(dp))-1; i<rbits && pos>=0; pos--) {
-	    _vl_vsss_setbit(rwp,rbits,lsb, 8, dp[pos]); lsb+=8;
+    case 's': // string/no conversion
+	for (int i=0, lsb=0, posp=((int)strlen(dp))-1; i<rbits && posp>=0; --posp) {
+	    _vl_vsss_setbit(rwp,rbits,lsb, 8, dp[posp]); lsb+=8;
 	}
 	break;
-    default:  // Compile time should have found all errors before this
-	vl_fatal (__FILE__, __LINE__, "", "$value$plusargs format error");
-	break;
+    case 'e': //FALLTHRU - Unsupported
+    case 'f': //FALLTHRU - Unsupported
+    case 'g': //FALLTHRU - Unsupported
+    default:  // Other simulators simply return 0 in these cases and don't error out
+	return 0;
     }
     _VL_CLEAN_INPLACE_W(rbits,rwp);
     return 1;
 }
+IData VL_VALUEPLUSARGS_INN(int, const string& ld, string& rdr) {
+    string prefix;
+    bool inPct = false;
+    bool done = false;
+    for (const char* posp = ld.c_str(); !done && *posp; ++posp) {
+	if (!inPct && posp[0]=='%') {
+	    inPct = true;
+	} else if (!inPct) {   // Normal text
+	    prefix += *posp;
+	} else { // Format character
+	    switch (tolower(*posp)) {
+	    case '%':
+		prefix += *posp;
+		inPct = false;
+		break;
+	    default:
+		done = true;
+		break;
+	    }
+	}
+    }
+    const string& match = VerilatedImp::argPlusMatch(prefix.c_str());
+    const char* dp = match.c_str() + 1 /*leading + */ + prefix.length();
+    if (match == "") return 0;
+    rdr = string(dp);
+    return 1;
+}
 
 const char* vl_mc_scan_plusargs(const char* prefixp) {
     const string& match = VerilatedImp::argPlusMatch(prefixp);
@@ -1142,7 +1226,7 @@ string VL_CVT_PACK_STR_NW(int lwords, WDataInP lwp) {
     bool start=true;
     char* destp = destout;
     int len = 0;
-    for (; lsb>=0; lsb--) {
+    for (; lsb>=0; --lsb) {
 	lsb = (lsb / 8) * 8; // Next digit
 	IData charval = (lwp[VL_BITWORD_I(lsb)]>>VL_BITBIT_I(lsb)) & 0xff;
 	if (!start || charval) {
@@ -1361,7 +1445,7 @@ void* VerilatedScope::exportFindError(int funcnum) const {
 
 void VerilatedScope::scopeDump() const {
     VL_PRINTF("    SCOPE %p: %s\n", this, name());
-    for (int i=0; i<m_funcnumMax; i++) {
+    for (int i=0; i<m_funcnumMax; ++i) {
 	if (m_callbacksp && m_callbacksp[i]) {
 	    VL_PRINTF("       DPI-EXPORT %p: %s\n",
 		      m_callbacksp[i], VerilatedImp::exportName(i));

include/verilated.h

@@ -349,7 +349,7 @@ extern WDataOutP VL_RANDOM_W(int obits, WDataOutP outwp);	///< Randomize a signa
 extern IData  VL_RAND_RESET_I(int obits);	///< Random reset a signal
 extern QData  VL_RAND_RESET_Q(int obits);	///< Random reset a signal
 extern WDataOutP VL_RAND_RESET_W(int obits, WDataOutP outwp);	///< Random reset a signal
-extern WDataOutP VL_ZERO_RESET_W(int obits, WDataOutP outwp);	///< Zero reset a signal
+extern WDataOutP VL_ZERO_RESET_W(int obits, WDataOutP outwp);	///< Zero reset a signal (slow - else use VL_ZERO_W)
 
 /// Math
 extern WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, bool is_modulus);
@@ -398,7 +398,7 @@ extern const char* vl_mc_scan_plusargs(const char* prefixp);  // PLIish
 //=========================================================================
 // Base macros
 
-/// Return true if data[bit] set
+/// Return true if data[bit] set; not 0/1 return, but 0/non-zero return.
 #define VL_BITISSET_I(data,bit) (data & (VL_UL(1)<<VL_BITBIT_I(bit)))
 #define VL_BITISSET_Q(data,bit) (data & (VL_ULL(1)<<VL_BITBIT_Q(bit)))
 #define VL_BITISSET_W(data,bit) (data[VL_BITWORD_I(bit)] & (VL_UL(1)<<VL_BITBIT_I(bit)))
@@ -433,6 +433,7 @@ static inline IData  VL_RTOIROUND_I_D(double lhs) { return ((vlsint32_t)(VL_ROUN
 // (Requires clean input)
 #define VL_SIGN_I(nbits,lhs)      ((lhs) >> VL_BITBIT_I((nbits) - VL_UL(1)))
 #define VL_SIGN_Q(nbits,lhs)      ((lhs) >> VL_BITBIT_Q((nbits) - VL_ULL(1)))
+#define VL_SIGN_W(nbits,rwp)      ((rwp)[VL_BITWORD_I((nbits)-VL_UL(1))] >> VL_BITBIT_I((nbits)-VL_UL(1)))
 #define VL_SIGNONES_I(nbits,lhs)  (-(VL_SIGN_I(nbits,lhs)))
 
 // Sign bit extended up to MSB, doesn't include unsigned portion
@@ -504,17 +505,28 @@ static inline WDataOutP _VL_CLEAN_INPLACE_W(int obits, WDataOutP owp) {
 }
 static inline WDataOutP VL_CLEAN_WW(int obits, int, WDataOutP owp, WDataInP lwp){
     int words = VL_WORDS_I(obits);
-    for (int i=0; (i < (words-1)); i++) owp[i] = lwp[i];
+    for (int i=0; (i < (words-1)); ++i) owp[i] = lwp[i];
     owp[words-1] = lwp[words-1] & VL_MASK_I(obits);
     return(owp);
 }
+static inline WDataOutP VL_ZERO_W(int obits, WDataOutP owp) {
+    int words = VL_WORDS_I(obits);
+    for (int i=0; i < words; ++i) owp[i] = 0;
+    return owp;
+}
+static inline WDataOutP VL_ALLONES_W(int obits, WDataOutP owp) {
+    int words = VL_WORDS_I(obits);
+    for (int i=0; (i < (words-1)); ++i) owp[i] = ~VL_UL(0);
+    owp[words-1] = VL_MASK_I(obits);
+    return owp;
+}
 
 // EMIT_RULE: VL_ASSIGN:  oclean=rclean; obits==lbits;
 // For now, we always have a clean rhs.
 // Note: If a ASSIGN isn't clean, use VL_ASSIGNCLEAN instead to do the same thing.
 static inline WDataOutP VL_ASSIGN_W(int obits, WDataOutP owp,WDataInP lwp){
     int words = VL_WORDS_I(obits);
-    for (int i=0; i < words; i++) owp[i] = lwp[i];
+    for (int i=0; i < words; ++i) owp[i] = lwp[i];
     return(owp);
 }
 
@@ -575,7 +587,7 @@ static inline void VL_ASSIGNBIT_WO(int, int bit, WDataOutP owp, IData) {
 }
 #define VL_ASSIGN_WSW(obits,owp,svar) { \
     int words = VL_WORDS_I(obits); \
-    for (int i=0; i < words; i++) owp[i] = svar.read().get_word(i); \
+    for (int i=0; i < words; ++i) owp[i] = svar.read().get_word(i); \
     owp[words-1] &= VL_MASK_I(obits); \
 }
 
@@ -584,7 +596,7 @@ static inline void VL_ASSIGNBIT_WO(int, int bit, WDataOutP owp, IData) {
 #define VL_ASSIGN_WSB(obits,owp,svar) {                       \
     int words = VL_WORDS_I(obits);                            \
     sc_biguint<obits> _butemp = (svar).read();                \
-    for (int i=0; i < words; i++) {                           \
+    for (int i=0; i < words; ++i) {                           \
         int msb = ((i+1)*VL_WORDSIZE) - 1;                    \
         msb = (msb >= obits) ? (obits-1) : msb;               \
         owp[i] = _butemp.range(msb,i*VL_WORDSIZE).to_uint();  \
@@ -611,7 +623,7 @@ static inline void VL_ASSIGNBIT_WO(int, int bit, WDataOutP owp, IData) {
 }
 #define VL_ASSIGN_SWW(obits,svar,rwp) { \
     sc_bv<obits> _bvtemp; \
-    for (int i=0; i < VL_WORDS_I(obits); i++) _bvtemp.set_word(i,rwp[i]); \
+    for (int i=0; i < VL_WORDS_I(obits); ++i) _bvtemp.set_word(i,rwp[i]); \
     svar.write(_bvtemp); \
 }
 
@@ -621,7 +633,7 @@ static inline void VL_ASSIGNBIT_WO(int, int bit, WDataOutP owp, IData) {
 #define VL_ASSIGN_SBQ(obits,svar,rd) { (svar).write(rd); }
 #define VL_ASSIGN_SBW(obits,svar,rwp) {             \
     sc_biguint<obits> _butemp;                      \
-    for (int i=0; i < VL_WORDS_I(obits); i++) {     \
+    for (int i=0; i < VL_WORDS_I(obits); ++i) {     \
         int msb = ((i+1)*VL_WORDSIZE) - 1;          \
         msb = (msb >= obits) ? (obits-1) : msb;     \
         _butemp.range(msb,i*VL_WORDSIZE) = rwp[i];  \
@@ -643,17 +655,17 @@ static inline void VL_ASSIGNBIT_WO(int, int bit, WDataOutP owp, IData) {
 static inline WDataOutP VL_EXTEND_WI(int obits, int, WDataOutP owp, IData ld) {
     // Note for extracts that obits != lbits
     owp[0] = ld;
-    for (int i=1; i < VL_WORDS_I(obits); i++) owp[i] = 0;
+    for (int i=1; i < VL_WORDS_I(obits); ++i) owp[i] = 0;
     return(owp);
 }
 static inline WDataOutP VL_EXTEND_WQ(int obits, int, WDataOutP owp, QData ld) {
     VL_SET_WQ(owp,ld);
-    for (int i=2; i < VL_WORDS_I(obits); i++) owp[i] = 0;
+    for (int i=2; i < VL_WORDS_I(obits); ++i) owp[i] = 0;
     return(owp);
 }
 static inline WDataOutP VL_EXTEND_WW(int obits, int lbits, WDataOutP owp, WDataInP lwp) {
-    for (int i=0; i < VL_WORDS_I(lbits); i++) owp[i] = lwp[i];
-    for (int i=VL_WORDS_I(lbits); i < VL_WORDS_I(obits); i++) owp[i] = 0;
+    for (int i=0; i < VL_WORDS_I(lbits); ++i) owp[i] = lwp[i];
+    for (int i=VL_WORDS_I(lbits); i < VL_WORDS_I(obits); ++i) owp[i] = 0;
     return(owp);
 }
 
@@ -672,22 +684,22 @@ static inline QData VL_EXTENDS_QQ(int, int lbits, QData lhs) {
 static inline WDataOutP VL_EXTENDS_WI(int obits, int lbits, WDataOutP owp, IData ld) {
     IData sign = VL_SIGNONES_I(lbits,ld);
     owp[0] = ld | (sign & ~VL_MASK_I(lbits));
-    for (int i=1; i < VL_WORDS_I(obits); i++) owp[i] = sign;
+    for (int i=1; i < VL_WORDS_I(obits); ++i) owp[i] = sign;
     return(owp);
 }
 static inline WDataOutP VL_EXTENDS_WQ(int obits, int lbits, WDataOutP owp, QData ld) {
     VL_SET_WQ(owp,ld);
     IData sign = VL_SIGNONES_I(lbits,owp[1]);
     owp[1] |= sign & ~VL_MASK_I(lbits);
-    for (int i=2; i < VL_WORDS_I(obits); i++) owp[i] = sign;
+    for (int i=2; i < VL_WORDS_I(obits); ++i) owp[i] = sign;
     return(owp);
 }
 static inline WDataOutP VL_EXTENDS_WW(int obits, int lbits, WDataOutP owp, WDataInP lwp) {
-    for (int i=0; i < VL_WORDS_I(lbits)-1; i++) owp[i] = lwp[i];
+    for (int i=0; i < VL_WORDS_I(lbits)-1; ++i) owp[i] = lwp[i];
     int lmsw=VL_WORDS_I(lbits)-1;
     IData sign = VL_SIGNONES_I(lbits,lwp[lmsw]);
     owp[lmsw] = lwp[lmsw] | (sign & ~VL_MASK_I(lbits));
-    for (int i=VL_WORDS_I(lbits); i < VL_WORDS_I(obits); i++) owp[i] = sign;
+    for (int i=VL_WORDS_I(lbits); i < VL_WORDS_I(obits); ++i) owp[i] = sign;
     return(owp);
 }
 
@@ -700,7 +712,7 @@ static inline WDataOutP VL_EXTENDS_WW(int obits, int lbits, WDataOutP owp, WData
 static inline IData VL_REDAND_IW(int, int lbits, WDataInP lwp) {
     int words = VL_WORDS_I(lbits);
     IData combine=lwp[0];
-    for (int i=1; i < words-1; i++) combine &= lwp[i];
+    for (int i=1; i < words-1; ++i) combine &= lwp[i];
     combine &= ~VL_MASK_I(lbits) | lwp[words-1];
     return ((~combine)==0);
 }
@@ -710,7 +722,7 @@ static inline IData VL_REDAND_IW(int, int lbits, WDataInP lwp) {
 #define VL_REDOR_Q(lhs) (lhs!=0)
 static inline IData VL_REDOR_W(int words, WDataInP lwp) {
     IData equal=0;
-    for (int i=0; i < words; i++) equal |= lwp[i];
+    for (int i=0; i < words; ++i) equal |= lwp[i];
     return(equal!=0);
 }
 
@@ -762,7 +774,7 @@ static inline IData VL_REDXOR_64(QData r) {
 }
 static inline IData VL_REDXOR_W(int words, WDataInP lwp) {
     IData r = lwp[0];
-    for (int i=1; i < words; i++) r ^= lwp[i];
+    for (int i=1; i < words; ++i) r ^= lwp[i];
     return VL_REDXOR_32(r);
 }
 
@@ -780,7 +792,7 @@ static inline IData VL_COUNTONES_Q(QData lhs) {
 }
 static inline IData VL_COUNTONES_W(int words, WDataInP lwp) {
     IData r = 0;
-    for (int i=0; (i < words); i++) r+=VL_COUNTONES_I(lwp[i]);
+    for (int i=0; (i < words); ++i) r+=VL_COUNTONES_I(lwp[i]);
     return r;
 }
 
@@ -792,7 +804,7 @@ static inline IData VL_ONEHOT_Q(QData lhs) {
 }
 static inline IData VL_ONEHOT_W(int words, WDataInP lwp) {
     IData one=0;
-    for (int i=0; (i < words); i++) {
+    for (int i=0; (i < words); ++i) {
 	if (lwp[i]) {
 	    if (one) return 0;
 	    one = 1;
@@ -810,7 +822,7 @@ static inline IData VL_ONEHOT0_Q(QData lhs) {
 }
 static inline IData VL_ONEHOT0_W(int words, WDataInP lwp) {
     bool one=false;
-    for (int i=0; (i < words); i++) {
+    for (int i=0; (i < words); ++i) {
 	if (lwp[i]) {
 	    if (one) return 0;
 	    one = true;
@@ -825,21 +837,21 @@ static inline IData VL_CLOG2_I(IData lhs) {
     if (VL_UNLIKELY(!lhs)) return 0;
     lhs--;
     int shifts=0;
-    for (; lhs!=0; shifts++) lhs = lhs >> 1;
+    for (; lhs!=0; ++shifts) lhs = lhs >> 1;
     return shifts;
 }
 static inline IData VL_CLOG2_Q(QData lhs) {
     if (VL_UNLIKELY(!lhs)) return 0;
     lhs--;
     int shifts=0;
-    for (; lhs!=0; shifts++) lhs = lhs >> VL_ULL(1);
+    for (; lhs!=0; ++shifts) lhs = lhs >> VL_ULL(1);
     return shifts;
 }
 static inline IData VL_CLOG2_W(int words, WDataInP lwp) {
     IData adjust = (VL_COUNTONES_W(words,lwp)==1) ? 0 : 1;
-    for (int i=words-1; i>=0; i--) {
+    for (int i=words-1; i>=0; --i) {
 	if (VL_UNLIKELY(lwp[i])) {  // Shorter worst case if predict not taken
-	    for (int bit=31; bit>=0; bit--) {
+	    for (int bit=31; bit>=0; --bit) {
 		if (VL_UNLIKELY(VL_BITISSET_I(lwp[i],bit))) {
 		    return i*VL_WORDSIZE + bit + adjust;
 		}
@@ -852,9 +864,9 @@ static inline IData VL_CLOG2_W(int words, WDataInP lwp) {
 
 static inline IData VL_MOSTSETBITP1_W(int words, WDataInP lwp) {
     // MSB set bit plus one; similar to FLS.  0=value is zero
-    for (int i=words-1; i>=0; i--) {
+    for (int i=words-1; i>=0; --i) {
 	if (VL_UNLIKELY(lwp[i])) {  // Shorter worst case if predict not taken
-	    for (int bit=31; bit>=0; bit--) {
+	    for (int bit=31; bit>=0; --bit) {
 		if (VL_UNLIKELY(VL_BITISSET_I(lwp[i],bit))) {
 		    return i*VL_WORDSIZE + bit + 1;
 		}
@@ -870,33 +882,33 @@ static inline IData VL_MOSTSETBITP1_W(int words, WDataInP lwp) {
 
 // EMIT_RULE: VL_AND:  oclean=lclean||rclean; obits=lbits; lbits==rbits;
 static inline WDataOutP VL_AND_W(int words, WDataOutP owp,WDataInP lwp,WDataInP rwp){
-    for (int i=0; (i < words); i++) owp[i] = (lwp[i] & rwp[i]);
+    for (int i=0; (i < words); ++i) owp[i] = (lwp[i] & rwp[i]);
     return(owp);
 }
 // EMIT_RULE: VL_OR:   oclean=lclean&&rclean; obits=lbits; lbits==rbits;
 static inline WDataOutP VL_OR_W(int words, WDataOutP owp,WDataInP lwp,WDataInP rwp){
-    for (int i=0; (i < words); i++) owp[i] = (lwp[i] | rwp[i]);
+    for (int i=0; (i < words); ++i) owp[i] = (lwp[i] | rwp[i]);
     return(owp);
 }
 // EMIT_RULE: VL_CHANGEXOR:  oclean=1; obits=32; lbits==rbits;
 static inline IData VL_CHANGEXOR_W(int words, WDataInP lwp,WDataInP rwp){
     IData od = 0;
-    for (int i=0; (i < words); i++) od |= (lwp[i] ^ rwp[i]);
+    for (int i=0; (i < words); ++i) od |= (lwp[i] ^ rwp[i]);
     return(od);
 }
 // EMIT_RULE: VL_XOR:  oclean=lclean&&rclean; obits=lbits; lbits==rbits;
 static inline WDataOutP VL_XOR_W(int words, WDataOutP owp,WDataInP lwp,WDataInP rwp){
-    for (int i=0; (i < words); i++) owp[i] = (lwp[i] ^ rwp[i]);
+    for (int i=0; (i < words); ++i) owp[i] = (lwp[i] ^ rwp[i]);
     return(owp);
 }
 // EMIT_RULE: VL_XNOR:  oclean=dirty; obits=lbits; lbits==rbits;
 static inline WDataOutP VL_XNOR_W(int words, WDataOutP owp,WDataInP lwp,WDataInP rwp){
-    for (int i=0; (i < words); i++) owp[i] = (lwp[i] ^ ~rwp[i]);
+    for (int i=0; (i < words); ++i) owp[i] = (lwp[i] ^ ~rwp[i]);
     return(owp);
 }
 // EMIT_RULE: VL_NOT:  oclean=dirty; obits=lbits;
 static inline WDataOutP VL_NOT_W(int words, WDataOutP owp,WDataInP lwp) {
-    for (int i=0; i < words; i++) owp[i] = ~(lwp[i]);
+    for (int i=0; i < words; ++i) owp[i] = ~(lwp[i]);
     return(owp);
 }
 
@@ -918,7 +930,7 @@ static inline WDataOutP VL_NOT_W(int words, WDataOutP owp,WDataInP lwp) {
 // Output clean, <lhs> AND <rhs> MUST BE CLEAN
 static inline IData VL_EQ_W(int words, WDataInP lwp, WDataInP rwp) {
     int nequal=0;
-    for (int i=0; (i < words); i++) nequal |= (lwp[i] ^ rwp[i]);
+    for (int i=0; (i < words); ++i) nequal |= (lwp[i] ^ rwp[i]);
     return(nequal==0);
 }
 
@@ -1012,7 +1024,7 @@ static inline int _VL_CMPS_W(int lbits, WDataInP lwp, WDataInP rwp) {
 
 static inline WDataOutP VL_ADD_W(int words, WDataOutP owp,WDataInP lwp,WDataInP rwp){
     QData carry = 0;
-    for (int i=0; i<words; i++) {
+    for (int i=0; i<words; ++i) {
 	carry = carry + (QData)(lwp[i]) + (QData)(rwp[i]);
 	owp[i] = (carry & VL_ULL(0xffffffff));
 	carry = (carry >> VL_ULL(32)) & VL_ULL(0xffffffff);
@@ -1022,7 +1034,7 @@ static inline WDataOutP VL_ADD_W(int words, WDataOutP owp,WDataInP lwp,WDataInP
 
 static inline WDataOutP VL_SUB_W(int words, WDataOutP owp,WDataInP lwp,WDataInP rwp){
     QData carry = 0;
-    for (int i=0; i<words; i++) {
+    for (int i=0; i<words; ++i) {
 	carry = carry + (QData)(lwp[i]) + (QData)(IData)(~rwp[i]);
 	if (i==0) carry++;  // Negation of temp2
 	owp[i] = (carry & VL_ULL(0xffffffff));
@@ -1039,7 +1051,7 @@ static inline QData  VL_NEGATE_Q(QData data) { return -data; }
 
 static inline WDataOutP VL_NEGATE_W(int words, WDataOutP owp,WDataInP lwp){
     QData carry = 0;
-    for (int i=0; i<words; i++) {
+    for (int i=0; i<words; ++i) {
 	carry = carry + (QData)(IData)(~lwp[i]);
 	if (i==0) carry++;  // Negation of temp2
 	owp[i] = (carry & VL_ULL(0xffffffff));
@@ -1049,11 +1061,11 @@ static inline WDataOutP VL_NEGATE_W(int words, WDataOutP owp,WDataInP lwp){
 }
 
 static inline WDataOutP VL_MUL_W(int words, WDataOutP owp,WDataInP lwp,WDataInP rwp){
-    for (int i=0; i<words; i++) owp[i] = 0;
-    for (int lword=0; lword<words; lword++) {
-	for (int rword=0; rword<words; rword++) {
+    for (int i=0; i<words; ++i) owp[i] = 0;
+    for (int lword=0; lword<words; ++lword) {
+	for (int rword=0; rword<words; ++rword) {
 	    QData mul = (QData)(lwp[lword]) * (QData)(rwp[rword]);
-	    for (int qword=lword+rword; qword<words; qword++) {
+	    for (int qword=lword+rword; qword<words; ++qword) {
 		mul += (QData)(owp[qword]);
 		owp[qword] = (mul & VL_ULL(0xffffffff));
 		mul = (mul >> VL_ULL(32)) & VL_ULL(0xffffffff);
@@ -1077,8 +1089,10 @@ static inline QData VL_MULS_QQQ(int,int lbits,int, QData lhs,QData rhs) {
 
 static inline WDataOutP VL_MULS_WWW(int,int lbits,int, WDataOutP owp,WDataInP lwp,WDataInP rwp){
     int words = VL_WORDS_I(lbits);
-    IData lwstore[VL_MULS_MAX_WORDS]; // Fixed size, as MSVC++ doesn't allow [words] here
-    IData rwstore[VL_MULS_MAX_WORDS];
+    // cppcheck-suppress variableScope
+    WData lwstore[VL_MULS_MAX_WORDS]; // Fixed size, as MSVC++ doesn't allow [words] here
+    // cppcheck-suppress variableScope
+    WData rwstore[VL_MULS_MAX_WORDS];
     WDataInP lwusp = lwp;
     WDataInP rwusp = rwp;
     IData lneg = VL_SIGN_I(lbits,lwp[words-1]);
@@ -1097,7 +1111,7 @@ static inline WDataOutP VL_MULS_WWW(int,int lbits,int, WDataOutP owp,WDataInP lw
     owp[words-1] &= VL_MASK_I(lbits);  // Clean.  Note it's ok for the multiply to overflow into the sign bit
     if ((lneg ^ rneg) & 1) {      // Negate output  (not using NEGATE, as owp==lwp)
 	QData carry = 0;
-	for (int i=0; i<words; i++) {
+	for (int i=0; i<words; ++i) {
 	    carry = carry + (QData)(IData)(~owp[i]);
 	    if (i==0) carry++;  // Negation of temp2
 	    owp[i] = (carry & VL_ULL(0xffffffff));
@@ -1139,9 +1153,9 @@ static inline WDataOutP VL_DIVS_WWW(int lbits, WDataOutP owp,WDataInP lwp,WDataI
     IData lsign = VL_SIGN_I(lbits,lwp[words-1]);
     IData rsign = VL_SIGN_I(lbits,rwp[words-1]);
     // cppcheck-suppress variableScope
-    IData lwstore[VL_MULS_MAX_WORDS]; // Fixed size, as MSVC++ doesn't allow [words] here
+    WData lwstore[VL_MULS_MAX_WORDS]; // Fixed size, as MSVC++ doesn't allow [words] here
     // cppcheck-suppress variableScope
-    IData rwstore[VL_MULS_MAX_WORDS];
+    WData rwstore[VL_MULS_MAX_WORDS];
     WDataInP ltup = lwp;
     WDataInP rtup = rwp;
     if (lsign) { ltup = _VL_CLEAN_INPLACE_W(lbits, VL_NEGATE_W(VL_WORDS_I(lbits), lwstore, lwp)); }
@@ -1160,15 +1174,15 @@ static inline WDataOutP VL_MODDIVS_WWW(int lbits, WDataOutP owp,WDataInP lwp,WDa
     IData lsign = VL_SIGN_I(lbits,lwp[words-1]);
     IData rsign = VL_SIGN_I(lbits,rwp[words-1]);
     // cppcheck-suppress variableScope
-    IData lwstore[VL_MULS_MAX_WORDS]; // Fixed size, as MSVC++ doesn't allow [words] here
+    WData lwstore[VL_MULS_MAX_WORDS]; // Fixed size, as MSVC++ doesn't allow [words] here
     // cppcheck-suppress variableScope
-    IData rwstore[VL_MULS_MAX_WORDS];
+    WData rwstore[VL_MULS_MAX_WORDS];
     WDataInP ltup = lwp;
     WDataInP rtup = rwp;
     if (lsign) { ltup = _VL_CLEAN_INPLACE_W(lbits, VL_NEGATE_W(VL_WORDS_I(lbits), lwstore, lwp)); }
     if (rsign) { rtup = _VL_CLEAN_INPLACE_W(lbits, VL_NEGATE_W(VL_WORDS_I(lbits), rwstore, rwp)); }
     if (lsign) {  // Only dividend sign matters for modulus
-	IData qNoSign[VL_MULS_MAX_WORDS];
+	WData qNoSign[VL_MULS_MAX_WORDS];
 	VL_MODDIV_WWW(lbits,qNoSign,ltup,rtup);
 	_VL_CLEAN_INPLACE_W(lbits, VL_NEGATE_W(VL_WORDS_I(lbits), owp, qNoSign));
 	return owp;
@@ -1184,7 +1198,7 @@ static inline IData VL_POW_III(int, int, int rbits, IData lhs, IData rhs) {
     if (VL_UNLIKELY(lhs==0)) return 0;
     IData power = lhs;
     IData out = 1;
-    for (int i=0; i<rbits; i++) {
+    for (int i=0; i<rbits; ++i) {
 	if (i>0) power = power*power;
 	if (rhs & (VL_ULL(1)<<i)) out *= power;
     }
@@ -1195,12 +1209,13 @@ static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) {
     if (VL_UNLIKELY(lhs==0)) return 0;
     QData power = lhs;
     QData out = VL_ULL(1);
-    for (int i=0; i<rbits; i++) {
+    for (int i=0; i<rbits; ++i) {
 	if (i>0) power = power*power;
 	if (rhs & (VL_ULL(1)<<i)) out *= power;
     }
     return out;
 }
+WDataOutP VL_POW_WWW(int obits, int, int rbits, WDataOutP owp, WDataInP lwp, WDataInP rwp);
 
 #define VL_POWSS_QQI(obits,lbits,rbits,lhs,rhs,lsign,rsign) VL_POWSS_QQQ(obits,lbits,rbits,lhs,rhs,lsign,rsign)
 
@@ -1209,28 +1224,28 @@ static inline IData VL_POWSS_III(int obits, int, int rbits, IData lhs, IData rhs
     if (rsign && VL_SIGN_I(rbits, rhs)) {
 	if (lhs==0) return 0;	// "X"
 	else if (lhs==1) return 1;
-	else if (lsign && lhs==VL_MASK_I(obits)) {  //-1
+	else if (lsign && lhs==VL_MASK_I(obits)) {  // -1
 	    if (rhs & 1) return VL_MASK_I(obits);  // -1^odd=-1
 	    else return 1; // -1^even=1
 	}
 	return 0;
     }
-    return VL_POW_III(obits, obits, rbits, lhs, rhs);
+    return VL_POW_III(obits, rbits, rbits, lhs, rhs);
 }
-
 static inline QData VL_POWSS_QQQ(int obits, int, int rbits, QData lhs, QData rhs, bool lsign, bool rsign) {
     if (VL_UNLIKELY(rhs==0)) return 1;
     if (rsign && VL_SIGN_I(rbits, rhs)) {
 	if (lhs==0) return 0;	// "X"
 	else if (lhs==1) return 1;
-	else if (lsign && lhs==VL_MASK_I(obits)) {  //-1
+	else if (lsign && lhs==VL_MASK_I(obits)) {  // -1
 	    if (rhs & 1) return VL_MASK_I(obits);  // -1^odd=-1
 	    else return 1; // -1^even=1
 	}
 	return 0;
     }
-    return VL_POW_QQQ(obits, obits, rbits, lhs, rhs);
+    return VL_POW_QQQ(obits, rbits, rbits, lhs, rhs);
 }
+WDataOutP VL_POWSS_WWW(int obits, int, int rbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, bool lsign, bool rsign);
 
 //===================================================================
 // Concat/replication
@@ -1285,13 +1300,13 @@ static inline void _VL_INSERT_WW(int, WDataOutP owp, WDataInP lwp, int hbit, int
     int words = VL_WORDS_I(hbit-lbit+1);
     if (hoffset==VL_SIZEBITS_I && loffset==0) {
 	// Fast and common case, word based insertion
-	for (int i=0; i<words; i++) {
+	for (int i=0; i<words; ++i) {
 	    owp[lword+i] = lwp[i];
 	}
     }
     else if (loffset==0) {
 	// Non-32bit, but nicely aligned, so stuff all but the last word
-	for (int i=0; i<(words-1); i++) {
+	for (int i=0; i<(words-1); ++i) {
 	    owp[lword+i] = lwp[i];
 	}
 	IData hinsmask = (VL_MASK_I(hoffset-0+1)); // Know it's not a full word as above fast case handled it
@@ -1303,7 +1318,7 @@ static inline void _VL_INSERT_WW(int, WDataOutP owp, WDataInP lwp, int hbit, int
 	int nbitsonright = 32-loffset;  // bits that end up in lword (know loffset!=0)
 	// Middle words
 	int hword = VL_BITWORD_I(hbit);
-	for (int i=0; i<words; i++) {
+	for (int i=0; i<words; ++i) {
 	    {	// Lower word
 		int oword = lword+i;
 		IData d = lwp[i]<<loffset;
@@ -1336,7 +1351,7 @@ static inline void _VL_INSERT_WQ(int obits, WDataOutP owp, QData ld, int hbit, i
 
 static inline IData VL_REPLICATE_III(int, int lbits, int, IData ld, IData rep) {
     IData returndata = ld;
-    for (unsigned i=1; i < rep; i++){
+    for (unsigned i=1; i < rep; ++i){
 	returndata = returndata << lbits;
 	returndata |= ld;
     }
@@ -1344,7 +1359,7 @@ static inline IData VL_REPLICATE_III(int, int lbits, int, IData ld, IData rep) {
 }
 static inline QData VL_REPLICATE_QII(int, int lbits, int, IData ld, IData rep) {
     QData returndata = ld;
-    for (unsigned i=1; i < rep; i++){
+    for (unsigned i=1; i < rep; ++i){
 	returndata = returndata << lbits;
 	returndata |= (QData)ld;
     }
@@ -1352,21 +1367,21 @@ static inline QData VL_REPLICATE_QII(int, int lbits, int, IData ld, IData rep) {
 }
 static inline WDataOutP VL_REPLICATE_WII(int obits, int lbits, int, WDataOutP owp, IData ld, IData rep) {
     owp[0] = ld;
-    for (unsigned i=1; i < rep; i++){
+    for (unsigned i=1; i < rep; ++i){
 	_VL_INSERT_WI(obits,owp,ld,i*lbits+lbits-1,i*lbits);
     }
     return(owp);
 }
 static inline WDataOutP VL_REPLICATE_WQI(int obits, int lbits, int, WDataOutP owp, QData ld, IData rep) {
     VL_SET_WQ(owp,ld);
-    for (unsigned i=1; i < rep; i++){
+    for (unsigned i=1; i < rep; ++i){
 	_VL_INSERT_WQ(obits,owp,ld,i*lbits+lbits-1,i*lbits);
     }
     return(owp);
 }
 static inline WDataOutP VL_REPLICATE_WWI(int obits, int lbits, int, WDataOutP owp, WDataInP lwp, IData rep) {
-    for (int i=0; i < VL_WORDS_I(lbits); i++) owp[i] = lwp[i];
-    for (unsigned i=1; i < rep; i++){
+    for (int i=0; i < VL_WORDS_I(lbits); ++i) owp[i] = lwp[i];
+    for (unsigned i=1; i < rep; ++i){
 	_VL_INSERT_WW(obits,owp,lwp,i*lbits+lbits-1,i*lbits);
     }
     return(owp);
@@ -1470,13 +1485,13 @@ static inline QData VL_STREAML_QQI(int, int lbits, int, QData ld, IData rd) {
 }
 
 static inline WDataOutP VL_STREAML_WWI(int, int lbits, int, WDataOutP owp, WDataInP lwp, IData rd) {
-    VL_ZERO_RESET_W(lbits, owp);
+    VL_ZERO_W(lbits, owp);
     // Slice size should never exceed the lhs width
     int ssize = (rd < (IData)lbits) ? rd : ((IData)lbits);
     for (int istart=0; istart<lbits; istart+=rd) {
 	int ostart=lbits-rd-istart;
         ostart = ostart > 0 ? ostart : 0;
-	for (int sbit=0; sbit<ssize && sbit<lbits-istart; sbit++) {
+	for (int sbit=0; sbit<ssize && sbit<lbits-istart; ++sbit) {
             // Extract a single bit from lwp and shift it to the correct
             // location for owp.
             WData bit= ((lwp[VL_BITWORD_I(istart+sbit)] >> VL_BITBIT_I(istart+sbit)) & 1) << VL_BITBIT_I(ostart+sbit);
@@ -1498,55 +1513,55 @@ static inline WDataOutP VL_STREAML_WWI(int, int lbits, int, WDataOutP owp, WData
 
 static inline WDataOutP VL_CONCAT_WII(int obits,int lbits,int rbits,WDataOutP owp,IData ld,IData rd) {
     owp[0] = rd;
-    for (int i=1; i < VL_WORDS_I(obits); i++) owp[i] = 0;
+    for (int i=1; i < VL_WORDS_I(obits); ++i) owp[i] = 0;
     _VL_INSERT_WI(obits,owp,ld,rbits+lbits-1,rbits);
     return(owp);
 }
 static inline WDataOutP VL_CONCAT_WWI(int obits,int lbits,int rbits,WDataOutP owp,WDataInP lwp, IData rd) {
     owp[0] = rd;
-    for (int i=1; i < VL_WORDS_I(obits); i++) owp[i] = 0;
+    for (int i=1; i < VL_WORDS_I(obits); ++i) owp[i] = 0;
     _VL_INSERT_WW(obits,owp,lwp,rbits+lbits-1,rbits);
     return(owp);
 }
 static inline WDataOutP VL_CONCAT_WIW(int obits,int lbits,int rbits,WDataOutP owp,IData ld, WDataInP rwp) {
-    for (int i=0; i < VL_WORDS_I(rbits); i++) owp[i] = rwp[i];
-    for (int i=VL_WORDS_I(rbits); i < VL_WORDS_I(obits); i++) owp[i] = 0;
+    for (int i=0; i < VL_WORDS_I(rbits); ++i) owp[i] = rwp[i];
+    for (int i=VL_WORDS_I(rbits); i < VL_WORDS_I(obits); ++i) owp[i] = 0;
     _VL_INSERT_WI(obits,owp,ld,rbits+lbits-1,rbits);
     return(owp);
 }
 static inline WDataOutP VL_CONCAT_WIQ(int obits,int lbits,int rbits,WDataOutP owp,IData ld,QData rd) {
     VL_SET_WQ(owp,rd);
-    for (int i=2; i < VL_WORDS_I(obits); i++) owp[i] = 0;
+    for (int i=2; i < VL_WORDS_I(obits); ++i) owp[i] = 0;
     _VL_INSERT_WI(obits,owp,ld,rbits+lbits-1,rbits);
     return(owp);
 }
 static inline WDataOutP VL_CONCAT_WQI(int obits,int lbits,int rbits,WDataOutP owp,QData ld,IData rd) {
     owp[0] = rd;
-    for (int i=1; i < VL_WORDS_I(obits); i++) owp[i] = 0;
+    for (int i=1; i < VL_WORDS_I(obits); ++i) owp[i] = 0;
     _VL_INSERT_WQ(obits,owp,ld,rbits+lbits-1,rbits);
     return(owp);
 }
 static inline WDataOutP VL_CONCAT_WQQ(int obits,int lbits,int rbits,WDataOutP owp,QData ld,QData rd) {
     VL_SET_WQ(owp,rd);
-    for (int i=2; i < VL_WORDS_I(obits); i++) owp[i] = 0;
+    for (int i=2; i < VL_WORDS_I(obits); ++i) owp[i] = 0;
     _VL_INSERT_WQ(obits,owp,ld,rbits+lbits-1,rbits);
     return(owp);
 }
 static inline WDataOutP VL_CONCAT_WWQ(int obits,int lbits,int rbits,WDataOutP owp,WDataInP lwp, QData rd) {
     VL_SET_WQ(owp,rd);
-    for (int i=2; i < VL_WORDS_I(obits); i++) owp[i] = 0;
+    for (int i=2; i < VL_WORDS_I(obits); ++i) owp[i] = 0;
     _VL_INSERT_WW(obits,owp,lwp,rbits+lbits-1,rbits);
     return(owp);
 }
 static inline WDataOutP VL_CONCAT_WQW(int obits,int lbits,int rbits,WDataOutP owp,QData ld, WDataInP rwp) {
-    for (int i=0; i < VL_WORDS_I(rbits); i++) owp[i] = rwp[i];
-    for (int i=VL_WORDS_I(rbits); i < VL_WORDS_I(obits); i++) owp[i] = 0;
+    for (int i=0; i < VL_WORDS_I(rbits); ++i) owp[i] = rwp[i];
+    for (int i=VL_WORDS_I(rbits); i < VL_WORDS_I(obits); ++i) owp[i] = 0;
     _VL_INSERT_WQ(obits,owp,ld,rbits+lbits-1,rbits);
     return(owp);
 }
 static inline WDataOutP VL_CONCAT_WWW(int obits,int lbits,int rbits,WDataOutP owp,WDataInP lwp, WDataInP rwp) {
-    for (int i=0; i < VL_WORDS_I(rbits); i++) owp[i] = rwp[i];
-    for (int i=VL_WORDS_I(rbits); i < VL_WORDS_I(obits); i++) owp[i] = 0;
+    for (int i=0; i < VL_WORDS_I(rbits); ++i) owp[i] = rwp[i];
+    for (int i=VL_WORDS_I(rbits); i < VL_WORDS_I(obits); ++i) owp[i] = 0;
     _VL_INSERT_WW(obits,owp,lwp,rbits+lbits-1,rbits);
     return(owp);
 }
@@ -1559,7 +1574,7 @@ static inline WDataOutP VL_CONCAT_WWW(int obits,int lbits,int rbits,WDataOutP ow
 static inline void _VL_SHIFTL_INPLACE_W(int obits,WDataOutP iowp,IData rd/*1 or 4*/) {
     int words = VL_WORDS_I(obits);
     IData linsmask = VL_MASK_I(rd);
-    for (int i=words-1; i>=1; i--) {
+    for (int i=words-1; i>=1; --i) {
 	iowp[i] = ((iowp[i]<<rd) & ~linsmask) | ((iowp[i-1] >> (32-rd)) & linsmask);
     }
     iowp[0] = ((iowp[0]<<rd) & ~linsmask);
@@ -1573,16 +1588,32 @@ static inline WDataOutP VL_SHIFTL_WWI(int obits,int,int,WDataOutP owp,WDataInP l
     int word_shift = VL_BITWORD_I(rd);
     int bit_shift = VL_BITBIT_I(rd);
     if (rd >= (IData)obits) {  // rd may be huge with MSB set
-	for (int i=0; i < VL_WORDS_I(obits); i++) owp[i] = 0;
+	for (int i=0; i < VL_WORDS_I(obits); ++i) owp[i] = 0;
     } else if (bit_shift==0) {  // Aligned word shift (<<0,<<32,<<64 etc)
-	for (int i=0; i < word_shift; i++) owp[i] = 0;
-	for (int i=word_shift; i < VL_WORDS_I(obits); i++) owp[i] = lwp[i-word_shift];
+	for (int i=0; i < word_shift; ++i) owp[i] = 0;
+	for (int i=word_shift; i < VL_WORDS_I(obits); ++i) owp[i] = lwp[i-word_shift];
     } else {
-	for (int i=0; i < VL_WORDS_I(obits); i++) owp[i] = 0;
+	for (int i=0; i < VL_WORDS_I(obits); ++i) owp[i] = 0;
 	_VL_INSERT_WW(obits,owp,lwp,obits-1,rd);
     }
     return(owp);
 }
+static inline WDataOutP VL_SHIFTL_WWW(int obits,int lbits,int rbits,WDataOutP owp,WDataInP lwp, WDataInP rwp) {
+    for (int i=1; i < VL_WORDS_I(rbits); ++i) {
+	if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more
+	    return VL_ZERO_W(obits, owp);
+	}
+    }
+    return VL_SHIFTL_WWI(obits,lbits,32,owp,lwp,rwp[0]);
+}
+static inline IData VL_SHIFTL_IIW(int obits,int,int rbits,IData lhs, WDataInP rwp) {
+    for (int i=1; i < VL_WORDS_I(rbits); ++i) {
+	if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more
+	    return 0;
+	}
+    }
+    return VL_CLEAN_II(obits,obits,lhs<<rwp[0]);
+}
 
 // EMIT_RULE: VL_SHIFTR:  oclean=lclean; rclean==clean;
 // Important: Unlike most other funcs, the shift might well be a computed
@@ -1591,27 +1622,43 @@ static inline WDataOutP VL_SHIFTR_WWI(int obits,int,int,WDataOutP owp,WDataInP l
     int word_shift = VL_BITWORD_I(rd);  // Maybe 0
     int bit_shift = VL_BITBIT_I(rd);
     if (rd >= (IData)obits) {  // rd may be huge with MSB set
-	for (int i=0; i < VL_WORDS_I(obits); i++) owp[i] = 0;
+	for (int i=0; i < VL_WORDS_I(obits); ++i) owp[i] = 0;
     } else if (bit_shift==0) {  // Aligned word shift (>>0,>>32,>>64 etc)
 	int copy_words = (VL_WORDS_I(obits)-word_shift);
-	for (int i=0; i < copy_words; i++) owp[i] = lwp[i+word_shift];
-	for (int i=copy_words; i < VL_WORDS_I(obits); i++) owp[i] = 0;
+	for (int i=0; i < copy_words; ++i) owp[i] = lwp[i+word_shift];
+	for (int i=copy_words; i < VL_WORDS_I(obits); ++i) owp[i] = 0;
     } else {
 	int loffset = rd & VL_SIZEBITS_I;
 	int nbitsonright = 32-loffset;  // bits that end up in lword (know loffset!=0)
 	// Middle words
 	int words = VL_WORDS_I(obits-rd);
-	for (int i=0; i<words; i++) {
+	for (int i=0; i<words; ++i) {
 	    owp[i] = lwp[i+word_shift]>>loffset;
 	    int upperword = i+word_shift+1;
 	    if (upperword < VL_WORDS_I(obits)) {
 		owp[i] |= lwp[upperword]<< nbitsonright;
 	    }
 	}
-	for (int i=words; i<VL_WORDS_I(obits); i++) owp[i]=0;
+	for (int i=words; i<VL_WORDS_I(obits); ++i) owp[i]=0;
     }
     return(owp);
 }
+static inline WDataOutP VL_SHIFTR_WWW(int obits,int lbits,int rbits,WDataOutP owp,WDataInP lwp, WDataInP rwp) {
+    for (int i=1; i < VL_WORDS_I(rbits); ++i) {
+	if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more
+	    return VL_ZERO_W(obits, owp);
+	}
+    }
+    return VL_SHIFTR_WWI(obits,lbits,32,owp,lwp,rwp[0]);
+}
+static inline IData VL_SHIFTR_IIW(int obits,int,int rbits,IData lhs, WDataInP rwp) {
+    for (int i=1; i < VL_WORDS_I(rbits); ++i) {
+	if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more
+	    return 0;
+	}
+    }
+    return VL_CLEAN_II(obits,obits,lhs>>rwp[0]);
+}
 
 // EMIT_RULE: VL_SHIFTRS:  oclean=false; lclean=clean, rclean==clean;
 static inline IData VL_SHIFTRS_III(int obits, int lbits, int, IData lhs, IData rhs) {
@@ -1637,20 +1684,20 @@ static inline WDataOutP VL_SHIFTRS_WWI(int obits,int lbits,int,WDataOutP owp,WDa
     int lmsw = VL_WORDS_I(obits)-1;
     IData sign = VL_SIGNONES_I(lbits,lwp[lmsw]);
     if (rd >= (IData)obits) {  // Shifting past end, sign in all of lbits
-	for (int i=0; i <= lmsw; i++) owp[i] = sign;
+	for (int i=0; i <= lmsw; ++i) owp[i] = sign;
 	owp[lmsw] &= VL_MASK_I(lbits);
     } else if (bit_shift==0) {  // Aligned word shift (>>0,>>32,>>64 etc)
 	int copy_words = (VL_WORDS_I(obits)-word_shift);
-	for (int i=0; i < copy_words; i++) owp[i] = lwp[i+word_shift];
+	for (int i=0; i < copy_words; ++i) owp[i] = lwp[i+word_shift];
 	if (copy_words>=0) owp[copy_words-1] |= ~VL_MASK_I(obits) & sign;
-	for (int i=copy_words; i < VL_WORDS_I(obits); i++) owp[i] = sign;
+	for (int i=copy_words; i < VL_WORDS_I(obits); ++i) owp[i] = sign;
 	owp[lmsw] &= VL_MASK_I(lbits);
     } else {
 	int loffset = rd & VL_SIZEBITS_I;
 	int nbitsonright = 32-loffset;  // bits that end up in lword (know loffset!=0)
 	// Middle words
 	int words = VL_WORDS_I(obits-rd);
-	for (int i=0; i<words; i++) {
+	for (int i=0; i<words; ++i) {
 	    owp[i] = lwp[i+word_shift]>>loffset;
 	    int upperword = i+word_shift+1;
 	    if (upperword < VL_WORDS_I(obits)) {
@@ -1658,11 +1705,49 @@ static inline WDataOutP VL_SHIFTRS_WWI(int obits,int lbits,int,WDataOutP owp,WDa
 	    }
 	}
 	if (words) owp[words-1] |= sign & ~VL_MASK_I(obits-loffset);
-	for (int i=words; i<VL_WORDS_I(obits); i++) owp[i] = sign;
+	for (int i=words; i<VL_WORDS_I(obits); ++i) owp[i] = sign;
 	owp[lmsw] &= VL_MASK_I(lbits);
     }
     return(owp);
 }
+static inline WDataOutP VL_SHIFTRS_WWW(int obits,int lbits,int rbits,WDataOutP owp,WDataInP lwp, WDataInP rwp) {
+    for (int i=1; i < VL_WORDS_I(rbits); ++i) {
+	if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more
+	    int lmsw = VL_WORDS_I(obits)-1;
+	    IData sign = VL_SIGNONES_I(lbits,lwp[lmsw]);
+	    for (int i=0; i <= lmsw; ++i) owp[i] = sign;
+	    owp[lmsw] &= VL_MASK_I(lbits);
+	    return owp;
+	}
+    }
+    return VL_SHIFTRS_WWI(obits,lbits,32,owp,lwp,rwp[0]);
+}
+static inline IData VL_SHIFTRS_IIW(int obits,int lbits,int rbits,IData lhs, WDataInP rwp) {
+    for (int i=1; i < VL_WORDS_I(rbits); ++i) {
+	if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more
+	    IData sign    = -(lhs >> (lbits-1)); // ffff_ffff if negative
+	    return VL_CLEAN_II(obits,obits,sign);
+	}
+    }
+    return VL_SHIFTRS_III(obits,lbits,32,lhs,rwp[0]);
+}
+static inline QData VL_SHIFTRS_QQW(int obits,int lbits,int rbits,QData lhs, WDataInP rwp) {
+    for (int i=1; i < VL_WORDS_I(rbits); ++i) {
+	if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more
+	    QData sign    = -(lhs >> (lbits-1)); // ffff_ffff if negative
+	    return VL_CLEAN_QQ(obits,obits,sign);
+	}
+    }
+    return VL_SHIFTRS_QQI(obits,lbits,32,lhs,rwp[0]);
+}
+static inline IData VL_SHIFTRS_IIQ(int obits,int lbits,int rbits,IData lhs, QData rhs) {
+    WData rwp[2]; VL_SET_WQ(rwp,rhs);
+    return VL_SHIFTRS_IIW(obits,lbits,rbits,lhs,rwp);
+}
+static inline QData VL_SHIFTRS_QQQ(int obits,int lbits,int rbits,QData lhs, QData rhs) {
+    WData rwp[2]; VL_SET_WQ(rwp,rhs);
+    return VL_SHIFTRS_QQW(obits,lbits,rbits,lhs,rwp);
+}
 
 //===================================================================
 // Bit selection
@@ -1728,25 +1813,25 @@ static inline WDataOutP VL_SEL_WWII(int obits,int lbits,int,int,WDataOutP owp,WD
     int msb = lsb+width-1;
     int word_shift = VL_BITWORD_I(lsb);
     if (VL_UNLIKELY(msb>lbits)) { // Outside bounds,
-	for (int i=0; i<VL_WORDS_I(obits)-1; i++) owp[i] = ~0;
+	for (int i=0; i<VL_WORDS_I(obits)-1; ++i) owp[i] = ~0;
 	owp[VL_WORDS_I(obits)-1] = VL_MASK_I(obits);
     } else if (VL_BITBIT_I(lsb)==0) {
 	// Just a word extract
-	for (int i=0; i<VL_WORDS_I(obits); i++) owp[i] = lwp[i+word_shift];
+	for (int i=0; i<VL_WORDS_I(obits); ++i) owp[i] = lwp[i+word_shift];
     } else {
 	// Not a _VL_INSERT because the bits come from any bit number and goto bit 0
 	int loffset = lsb & VL_SIZEBITS_I;
 	int nbitsfromlow = 32-loffset;  // bits that end up in lword (know loffset!=0)
 	// Middle words
 	int words = VL_WORDS_I(msb-lsb+1);
-	for (int i=0; i<words; i++) {
+	for (int i=0; i<words; ++i) {
 	    owp[i] = lwp[i+word_shift]>>loffset;
 	    int upperword = i+word_shift+1;
 	    if (upperword <= (int)VL_BITWORD_I(msb)) {
 		owp[i] |= lwp[upperword]<< nbitsfromlow;
 	    }
 	}
-	for (int i=words; i<VL_WORDS_I(obits); i++) owp[i]=0;
+	for (int i=words; i<VL_WORDS_I(obits); ++i) owp[i]=0;
     }
     return owp;
 }
@@ -1791,7 +1876,7 @@ static inline void VL_ASSIGNSEL_WIIW(int obits, int lsb, WDataOutP owp, WDataInP
 static inline WDataOutP VL_COND_WIWW(int obits, int, int, int,
 				     WDataOutP owp, int cond, WDataInP w1p, WDataInP w2p) {
     int words = VL_WORDS_I(obits);
-    for (int i=0; i < words; i++) owp[i] = cond ? w1p[i] : w2p[i];
+    for (int i=0; i < words; ++i) owp[i] = cond ? w1p[i] : w2p[i];
     return(owp);
 }
 
@@ -1824,7 +1909,7 @@ inline IData VL_VALUEPLUSARGS_II(int rbits, const char* prefixp, char fmt, IData
 // If changing the number of functions here, also change EMITCINLINES_NUM_CONSTW
 
 #define _END(obits,wordsSet) \
-    for(int i=(wordsSet);i<VL_WORDS_I(obits);i++) o[i] = (IData)0x0; \
+    for(int i=(wordsSet);i<VL_WORDS_I(obits);++i) o[i] = (IData)0x0; \
     return o
 
 #define VL_HAVE_CONST_W_1X

include/verilated_cov.cpp

@@ -50,7 +50,7 @@ public:  // But only local to this file
     // CONSTRUCTORS
     // Derived classes should call zero() in their constructor
     VerilatedCovImpItem() {
-	for (int i=0; i<MAX_KEYS; i++) {
+	for (int i=0; i<MAX_KEYS; ++i) {
 	    m_keys[i]=KEY_UNDEF;
 	    m_vals[i]=0;
 	}
@@ -130,7 +130,7 @@ private:
     string dequote(const string& text) {
 	// Quote any special characters
 	string rtn;
-	for (const char* pos = text.c_str(); *pos; pos++) {
+	for (const char* pos = text.c_str(); *pos; ++pos) {
 	    if (!isprint(*pos) || *pos=='%' || *pos=='"') {
 		char hex[10]; sprintf(hex,"%%%02X",pos[0]);
 		rtn += hex;
@@ -194,7 +194,7 @@ private:
 	return out;
     }
     bool itemMatchesString(VerilatedCovImpItem* itemp, const string& match) {
-	for (int i=0; i<MAX_KEYS; i++) {
+	for (int i=0; i<MAX_KEYS; ++i) {
 	    if (itemp->m_keys[i] != KEY_UNDEF) {
 		// We don't compare keys, only values
 		string val = m_indexValues[itemp->m_vals[i]];
@@ -274,15 +274,15 @@ public:
 
 	// Keys -> strings
 	string keys[MAX_KEYS];
-	for (int i=0; i<MAX_KEYS; i++) {
+	for (int i=0; i<MAX_KEYS; ++i) {
 	    if (ckeyps[i] && ckeyps[i][0]) {
 		keys[i] = ckeyps[i];
 	    }
 	}
 	// Ignore empty keys
-	for (int i=0; i<MAX_KEYS; i++) {
+	for (int i=0; i<MAX_KEYS; ++i) {
 	    if (keys[i]!="") {
-		for (int j=i+1; j<MAX_KEYS; j++) {
+		for (int j=i+1; j<MAX_KEYS; ++j) {
 		    if (keys[i] == keys[j]) {  // Duplicate key.  Keep the last one
 			keys[i] = "";
 			break;
@@ -292,7 +292,7 @@ public:
 	}
 	// Insert the values
 	int addKeynum=0;
-	for (int i=0; i<MAX_KEYS; i++) {
+	for (int i=0; i<MAX_KEYS; ++i) {
 	    const string key = keys[i];
 	    if (keys[i]!="") {
 		const string val = valps[i];
@@ -334,7 +334,7 @@ public:
 	    string hier;
 	    bool per_instance = false;
 
-	    for (int i=0; i<MAX_KEYS; i++) {
+	    for (int i=0; i<MAX_KEYS; ++i) {
 		if (itemp->m_keys[i] != KEY_UNDEF) {
 		    string key = VerilatedCovKey::shortKey(m_indexValues[itemp->m_keys[i]]);
 		    string val = m_indexValues[itemp->m_vals[i]];

include/verilated_cov.h

@@ -60,9 +60,9 @@ using namespace std;
 ///
 ///	vluint32_t m_cases[10];
 ///	constructor {
-///	    for (int i=0; i<10; i++) { m_cases[i]=0; }
+///	    for (int i=0; i<10; ++i) { m_cases[i]=0; }
 ///     }
-///	for (int i=0; i<10; i++) {
+///	for (int i=0; i<10; ++i) {
 ///		VL_COVER_INSERT(&m_cases[i], "comment", "Coverage Case", "i", cvtToNumStr(i));
 ///	}
 

include/verilated_dpi.h

@@ -37,25 +37,25 @@
 /// Return svBitVecVal from WData
 static inline void VL_SET_W_SVBV(int obits, WDataOutP owp, svBitVecVal* lwp) {
     int words = VL_WORDS_I(obits);
-    for (int i=0; i<words-1; i++) owp[i]=lwp[i];
+    for (int i=0; i<words-1; ++i) owp[i]=lwp[i];
     owp[words-1] = lwp[words-1] & VL_MASK_I(obits);
 }
 static inline void VL_SET_SVBV_W(int obits, svBitVecVal* owp, WDataInP lwp) {
     int words = VL_WORDS_I(obits);
-    for (int i=0; i<words-1; i++) owp[i]=lwp[i];
+    for (int i=0; i<words-1; ++i) owp[i]=lwp[i];
     owp[words-1] = lwp[words-1] & VL_MASK_I(obits);
 }
 static inline void VL_SET_W_SVLV(int obits, WDataOutP owp, svLogicVecVal* lwp) {
     // Note we ignore X/Z in svLogicVecVal
     int words = VL_WORDS_I(obits);
-    for (int i=0; i<words-1; i++) owp[i]=lwp[i].aval;
+    for (int i=0; i<words-1; ++i) owp[i]=lwp[i].aval;
     owp[words-1] = lwp[words-1].aval & VL_MASK_I(obits);
 }
 static inline void VL_SET_SVLV_W(int obits, svLogicVecVal* owp, WDataInP lwp) {
     // Note we don't create X/Z in svLogicVecVal
     int words = VL_WORDS_I(obits);
-    for (int i=0; i<words; i++) owp[i].bval=0;
-    for (int i=0; i<words-1; i++) owp[i].aval=lwp[i];
+    for (int i=0; i<words; ++i) owp[i].bval=0;
+    for (int i=0; i<words-1; ++i) owp[i].aval=lwp[i];
     owp[words-1].aval = lwp[words-1] & VL_MASK_I(obits);
 }
 

include/verilated_heavy.h

@@ -38,14 +38,14 @@
 
 extern string VL_CVT_PACK_STR_NW(int lwords, WDataInP lwp);
 inline string VL_CVT_PACK_STR_NQ(QData lhs) {
-    IData lw[2];  VL_SET_WQ(lw, lhs);
+    WData lw[2];  VL_SET_WQ(lw, lhs);
     return VL_CVT_PACK_STR_NW(2, lw);
 }
 inline string VL_CVT_PACK_STR_NN(const string& lhs) {
     return lhs;
 }
 inline string VL_CVT_PACK_STR_NI(IData lhs) {
-    IData lw[1];  lw[0] = lhs;
+    WData lw[1];  lw[0] = lhs;
     return VL_CVT_PACK_STR_NW(1, lw);
 }
 inline string VL_CONCATN_NNN(const string& lhs, const string& rhs) {
@@ -53,7 +53,7 @@ inline string VL_CONCATN_NNN(const string& lhs, const string& rhs) {
 }
 inline string VL_REPLICATEN_NNQ(int,int,int, const string& lhs, IData rep) {
     string out; out.reserve(lhs.length() * rep);
-    for (unsigned times=0; times<rep; times++) out += lhs;
+    for (unsigned times=0; times<rep; ++times) out += lhs;
     return out;
 }
 inline string VL_REPLICATEN_NNI(int obits,int lbits,int rbits, const string& lhs, IData rep) {
@@ -66,6 +66,19 @@ extern void VL_READMEM_N(bool hex, int width, int depth, int array_lsb, int fnwo
 extern IData VL_SSCANF_INX(int lbits, const string& ld, const char* formatp, ...);
 extern void VL_SFORMAT_X(int obits_ignored, string &output, const char* formatp, ...);
 extern string VL_SFORMATF_NX(const char* formatp, ...);
-extern IData VL_VALUEPLUSARGS_IN(int rbits, const char* prefixp, char fmt, string& ldr);
+extern IData VL_VALUEPLUSARGS_INW(int rbits, const string& ld, WDataOutP rdp);
+inline IData VL_VALUEPLUSARGS_INI(int rbits, const string& ld, IData& rdr) {
+    WData rwp[1];
+    IData got = VL_VALUEPLUSARGS_INW(rbits,ld,rwp);
+    if (got) rdr = rwp[0];
+    return got;
+}
+inline IData VL_VALUEPLUSARGS_INQ(int rbits, const string& ld, QData& rdr) {
+    WData rwp[2];
+    IData got = VL_VALUEPLUSARGS_INW(rbits,ld,rwp);
+    if (got) rdr = VL_SET_QW(rwp);
+    return got;
+}
+extern IData VL_VALUEPLUSARGS_INN(int, const string& ld, string& rdr);
 
 #endif // Guard

include/verilated_imp.h

@@ -97,7 +97,7 @@ public: // But only for verilated*.cpp
     }
     static void commandArgsAdd(int argc, const char** argv) {
 	if (!s_s.m_argVecLoaded) s_s.m_argVec.clear();
-	for (int i=0; i<argc; i++) s_s.m_argVec.push_back(argv[i]);
+	for (int i=0; i<argc; ++i) s_s.m_argVec.push_back(argv[i]);
 	s_s.m_argVecLoaded = true; // Can't just test later for empty vector, no arguments is ok
     }
     static string argPlusMatch(const char* prefixp) {
@@ -238,7 +238,7 @@ public: // But only for verilated*.cpp
 	    // Need to create more space in m_fdps and m_fdFree
 	    size_t start = s_s.m_fdps.size();
 	    s_s.m_fdps.resize(start*2);
-	    for (size_t i=start; i<start*2; i++) s_s.m_fdFree.push_back((IData)i);
+	    for (size_t i=start; i<start*2; ++i) s_s.m_fdFree.push_back((IData)i);
 	}
 	IData idx = s_s.m_fdFree.back(); s_s.m_fdFree.pop_back();
 	s_s.m_fdps[idx] = fp;

include/verilated_vcd_c.h

@@ -428,6 +428,15 @@ public:
     void dump (double timestamp) { dump((vluint64_t)timestamp); }
     void dump (vluint32_t timestamp) { dump((vluint64_t)timestamp); }
     void dump (int timestamp) { dump((vluint64_t)timestamp); }
+    /// Set time units (s/ms, defaults to ns)
+    /// See also VL_TIME_PRECISION, and VL_TIME_MULTIPLIER in verilated.h
+    void set_time_unit (const char* unit) { m_sptrace.set_time_unit(unit); }
+    void set_time_unit (const string& unit) { set_time_unit(unit.c_str()); }
+    /// Set time resolution (s/ms, defaults to ns)
+    /// See also VL_TIME_PRECISION, and VL_TIME_MULTIPLIER in verilated.h
+    void set_time_resolution (const char* unit) { m_sptrace.set_time_resolution(unit); }
+    void set_time_resolution (const string& unit) { set_time_resolution(unit.c_str()); }
+
     /// Internal class access
     inline VerilatedVcd* spTrace () { return &m_sptrace; };
 };

include/verilated_vpi.cpp

@@ -754,7 +754,7 @@ void vpi_get_value(vpiHandle object, p_vpi_value value_p) {
 		    vl_fatal(__FILE__,__LINE__,"", "vpi_get_value with more than VL_MULS_MAX_WORDS; increase and recompile");
 		}
 		WDataInP datap = ((IData*)(vop->varDatap()));
-		for (int i=0; i<words; i++) {
+		for (int i=0; i<words; ++i) {
 		    out[i].aval = datap[i];
 		    out[i].bval = 0;
 		}
@@ -791,7 +791,7 @@ void vpi_get_value(vpiHandle object, p_vpi_value value_p) {
 		  _VL_VPI_WARNING(__FILE__, __LINE__, "%s: Truncating string value of %s for %s as buffer size (%d, VL_MULS_MAX_WORDS=%d) is less than required (%d)",
 				  VL_FUNC, VerilatedVpiError::strFromVpiVal(value_p->format), vop->fullname(), outStrSz, VL_MULS_MAX_WORDS, bits);
 		}
-		for (i=0; i<bits; i++) {
+		for (i=0; i<bits; ++i) {
 		    char val = (datap[i>>3]>>(i&7))&1;
 		    outStr[bits-i-1] = val?'1':'0';
 		}
@@ -821,7 +821,7 @@ void vpi_get_value(vpiHandle object, p_vpi_value value_p) {
 				    VL_FUNC, VerilatedVpiError::strFromVpiVal(value_p->format), vop->fullname(), outStrSz, VL_MULS_MAX_WORDS, chars);
 		    chars = outStrSz;
 	        }
-		for (i=0; i<chars; i++) {
+		for (i=0; i<chars; ++i) {
                     div_t idx = div(i*3, 8);
 		    int val = datap[idx.quot];
                     if ((idx.quot+1)<bytes) {
@@ -882,7 +882,7 @@ void vpi_get_value(vpiHandle object, p_vpi_value value_p) {
 				  VL_FUNC, VerilatedVpiError::strFromVpiVal(value_p->format), vop->fullname(), outStrSz, VL_MULS_MAX_WORDS, chars);
 		  chars = outStrSz;
 		}
-		for (i=0; i<chars; i++) {
+		for (i=0; i<chars; ++i) {
 		    char val = (datap[i>>1]>>((i&1)<<2))&15;
                     static char hex[] = "0123456789abcdef";
                     if (i==(chars-1)) {
@@ -922,7 +922,7 @@ void vpi_get_value(vpiHandle object, p_vpi_value value_p) {
 				  vop->fullname(), outStrSz, VL_MULS_MAX_WORDS, bytes);
 		  bytes = outStrSz;
 		}
-		for (i=0; i<bytes; i++) {
+		for (i=0; i<bytes; ++i) {
 		    char val = datap[bytes-i-1];
                      // other simulators replace [leading?] zero chars with spaces, replicate here.
 		    outStr[i] = val?val:' ';
@@ -1007,7 +1007,7 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value value_p,
 	    case VLVT_WDATA: {
 		int words = VL_WORDS_I(vop->varp()->range().elements());
 		WDataOutP datap = ((IData*)(vop->varDatap()));
-		for (int i=0; i<words; i++) {
+		for (int i=0; i<words; ++i) {
 		    datap[i] = value_p->value.vector[i].aval;
                     if (i==(words-1)) {
 			datap[i] &= vop->mask();
@@ -1037,7 +1037,7 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value value_p,
 		int bits = vop->varp()->range().elements();
 		int len	 = strlen(value_p->value.str);
 		CData* datap = ((CData*)(vop->varDatap()));
-		for (int i=0; i<bits; i++) {
+		for (int i=0; i<bits; ++i) {
                     char set = (i < len)?(value_p->value.str[len-i-1]=='1'):0;
                     // zero bits 7:1 of byte when assigning to bit 0, else
                     // or in 1 if bit set
@@ -1067,7 +1067,7 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value value_p,
 		CData* datap = ((CData*)(vop->varDatap()));
                 div_t idx;
                 datap[0] = 0; // reset zero'th byte
-		for (int i=0; i<chars; i++) {
+		for (int i=0; i<chars; ++i) {
                     union {
 			char  byte[2];
                         short half;
@@ -1105,7 +1105,7 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value value_p,
                     datap[idx.quot+1] &= vop->mask_byte(idx.quot+1);
 		}
                 // zero off remaining top bytes
-                for (int i=idx.quot+2; i<bytes; i++) {
+                for (int i=idx.quot+2; i<bytes; ++i) {
 		    datap[i] = 0;
 		}
 		return object;
@@ -1155,7 +1155,7 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value value_p,
 		    val += 2;
 		}
 		int len = strlen(val);
-		for (int i=0; i<chars; i++) {
+		for (int i=0; i<chars; ++i) {
                     char hex;
                     // compute hex digit value
                     if (i < len) {
@@ -1197,7 +1197,7 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value value_p,
 		int bytes = VL_BYTES_I(vop->varp()->range().elements());
 		int len	  = strlen(value_p->value.str);
 		CData* datap = ((CData*)(vop->varDatap()));
-		for (int i=0; i<bytes; i++) {
+		for (int i=0; i<bytes; ++i) {
 		    datap[i] = (i < len)?value_p->value.str[len-i-1]:0; // prepend with 0 values before placing string the least signifcant bytes
 		}
 		return object;
@@ -1255,7 +1255,7 @@ void vpi_get_time(vpiHandle object, p_vpi_time time_p) {
     }
     if (time_p->type == vpiSimTime) {
 	QData qtime = VL_TIME_Q();
-	IData itime[2];
+	WData itime[2];
 	VL_SET_WQ(itime, qtime);
 	time_p->low = itime[0];
 	time_p->high = itime[1];

src/V3ActiveTop.cpp

@@ -108,7 +108,7 @@ private:
 	    // Move the active's contents to the other active
 	    UINFO(4,"   merge active "<<sensesp<<" into "<<wantp<<endl);
 	    if (nodep->sensesStorep()) {
-		if (sensesp != nodep->sensesStorep()) nodep->v3fatalSrc("sensesStore should have been deleted earlier if different\n");
+		if (sensesp != nodep->sensesStorep()) nodep->v3fatalSrc("sensesStore should have been deleted earlier if different");
 		sensesp->unlinkFrBack();
 		// There may be other references to same sense tree,
 		// we'll be removing all references when we get to them,

src/V3Assert.cpp

@@ -246,20 +246,10 @@ private:
 		    for (AstCaseItem* itemp = nodep->itemsp(); itemp; itemp=itemp->nextp()->castCaseItem()) {
 			for (AstNode* icondp = itemp->condsp(); icondp!=NULL; icondp=icondp->nextp()) {
 			    AstNode* onep;
-			    AstConst* iconstp = icondp->castConst();
-			    if (iconstp && iconstp->num().isFourState()
-				&& (nodep->casex() || nodep->casez() || nodep->caseInside())) {
-				V3Number nummask (itemp->fileline(), iconstp->width());
-				nummask.opBitsNonX(iconstp->num());
-				V3Number numval  (itemp->fileline(), iconstp->width());
-				numval.opBitsOne(iconstp->num());
-				AstNode* and1p = new AstAnd(itemp->fileline(), nodep->exprp()->cloneTree(false),
-							    new AstConst(itemp->fileline(), nummask));
-				AstNode* and2p = new AstAnd(itemp->fileline(),
-							    new AstConst(itemp->fileline(), numval),
-							    new AstConst(itemp->fileline(), nummask));
-				onep = AstEq::newTyped(itemp->fileline(), and1p, and2p);
-
+			    if (nodep->casex() || nodep->casez() || nodep->caseInside()) {
+				onep = AstEqWild::newTyped(itemp->fileline(),
+							   nodep->exprp()->cloneTree(false),
+							   icondp->cloneTree(false));
 			    } else {
 				onep = AstEq::newTyped(icondp->fileline(),
 						       nodep->exprp()->cloneTree(false),

src/V3Ast.h

@@ -1675,6 +1675,7 @@ public:
     virtual bool maybePointedTo() const { return true; }
     virtual AstNodeDType* virtRefDTypep() const { return NULL; } // Iff has a non-null refDTypep(), as generic node function
     virtual void virtRefDTypep(AstNodeDType* nodep) { }	// Iff has refDTypep(), set as generic node function
+    virtual bool similarDType(AstNodeDType* samep) const = 0;  // Assignable equivalence.  Call skipRefp() on this and samep before calling
     //
     // Changing the width may confuse the data type resolution, so must clear TypeTable cache after use.
     void widthForce(int width, int sized) { m_width=width; m_widthMin=sized; }
@@ -1724,6 +1725,9 @@ public:
     virtual int widthAlignBytes() const; // (Slow) recurses - Structure alignment 1,2,4 or 8 bytes (arrays affect this)
     virtual int widthTotalBytes() const; // (Slow) recurses - Width in bytes rounding up 1,2,4,8,12,...
     // op1 = members
+    virtual bool similarDType(AstNodeDType* samep) const {
+	return this==samep;  // We don't compare members, require exact equivalence
+    }
     AstMemberDType* membersp() const { return op1p()->castMemberDType(); } // op1 = AstMember list
     void addMembersp(AstNode* nodep) { addNOp1p(nodep); }
     bool packed() const { return m_packed; }
@@ -1754,7 +1758,7 @@ public:
     virtual void dump(ostream& str);
     virtual void dumpSmall(ostream& str);
     virtual const char* broken() const { BROKEN_RTN(!((m_refDTypep && !childDTypep() && m_refDTypep->brokeExists())
-						     || (!m_refDTypep && childDTypep()))); return NULL; }
+						      || (!m_refDTypep && childDTypep()))); return NULL; }
     virtual void cloneRelink() { if (m_refDTypep && m_refDTypep->clonep()) {
 	m_refDTypep = m_refDTypep->clonep();
     }}
@@ -1763,6 +1767,14 @@ public:
 	return (msb()==sp->msb()
 		&& subDTypep()==sp->subDTypep()
 		&& rangenp()->sameTree(sp->rangenp())); }  // HashedDT doesn't recurse, so need to check children
+    virtual bool similarDType(AstNodeDType* samep) const {
+	AstNodeArrayDType* sp = samep->castNodeArrayDType();
+	return (sp
+		&& type() == samep->type()
+		&& msb() == sp->msb()
+		&& rangenp()->sameTree(sp->rangenp())
+		&& subDTypep()->skipRefp()->similarDType(sp->subDTypep()->skipRefp()));
+    }
     virtual V3Hash sameHash() const { return V3Hash(V3Hash(m_refDTypep),V3Hash(msb()),V3Hash(lsb())); }
     AstNodeDType* getChildDTypep() const { return childDTypep(); }
     AstNodeDType* childDTypep() const { return op1p()->castNodeDType(); } // op1 = Range of variable

src/V3AstNodes.cpp

@@ -140,6 +140,13 @@ AstNodeBiop* AstLte::newTyped(FileLine* fl, AstNode* lhsp, AstNode* rhsp) {
     }
 }
 
+AstNodeBiop* AstEqWild::newTyped(FileLine* fl, AstNode* lhsp, AstNode* rhsp) {
+    if (lhsp->isDouble() && rhsp->isDouble()) {
+	return new AstEqD(fl, lhsp, rhsp);
+    } else {
+	return new AstEqWild(fl, lhsp, rhsp);
+    }
+}
 
 bool AstVar::isSigPublic() const {
     return (m_sigPublic || (v3Global.opt.allPublic() && !isTemp() && !isGenVar()));

src/V3AstNodes.h

@@ -180,6 +180,10 @@ public:
     virtual AstNodeDType* skipRefp() const { return subDTypep()->skipRefp(); }
     virtual AstNodeDType* skipRefToConstp() const { return subDTypep()->skipRefToConstp(); }
     virtual AstNodeDType* skipRefToEnump() const { return subDTypep()->skipRefToEnump(); }
+    virtual bool similarDType(AstNodeDType* samep) const {
+	AstParamTypeDType* sp = samep->castParamTypeDType();
+	return (sp && this->subDTypep()->skipRefp()->similarDType(sp->subDTypep()->skipRefp()));
+    }
     virtual int widthAlignBytes() const { return dtypep()->widthAlignBytes(); }
     virtual int widthTotalBytes() const { return dtypep()->widthTotalBytes(); }
     // METHODS
@@ -250,7 +254,9 @@ public:
 	m_uniqueNum = uniqueNumInc();
     }
     ASTNODE_NODE_FUNCS(DefImplicitDType)
-    virtual bool same(AstNode* samep) const { return m_uniqueNum==samep->castDefImplicitDType()->m_uniqueNum; }
+    virtual bool same(AstNode* samep) const { return m_uniqueNum==samep->castDefImplicitDType()->m_uniqueNum; } 
+    virtual bool similarDType(AstNodeDType* samep) const {
+	return type()==samep->type() && same(samep); }
     virtual V3Hash sameHash() const { return V3Hash(m_uniqueNum); }
     AstNodeDType* getChildDTypep() const { return childDTypep(); }
     AstNodeDType* childDTypep() const { return op1p()->castNodeDType(); } // op1 = Range of variable
@@ -392,6 +398,8 @@ public:
     virtual V3Hash sameHash() const { return V3Hash(V3Hash(m.m_keyword), V3Hash(m.m_nrange.hi())); }
     virtual bool same(AstNode* samep) const {  // width/widthMin/numeric compared elsewhere
 	return samep->castBasicDType()->m == m; }
+    virtual bool similarDType(AstNodeDType* samep) const {
+	return type()==samep->type() && same(samep); }
     virtual string name()	const { return m.m_keyword.ascii(); }
     virtual const char* broken() const { BROKEN_RTN(dtypep()!=this); return NULL; }
     AstRange*	rangep() 	const { return op1p()->castRange(); }	// op1 = Range of variable
@@ -456,6 +464,8 @@ public:
     }}
     virtual bool same(AstNode* samep) const {
 	return (m_refDTypep==samep->castConstDType()->m_refDTypep); }
+    virtual bool similarDType(AstNodeDType* samep) const {
+	return skipRefp()->similarDType(samep->skipRefp()); }
     virtual V3Hash sameHash() const { return V3Hash(m_refDTypep); }  // node's type() included elsewhere
     AstNodeDType* getChildDTypep() const { return childDTypep(); }
     AstNodeDType* childDTypep() const { return op1p()->castNodeDType(); } // op1 = Range of variable
@@ -499,6 +509,7 @@ public:
     virtual AstNodeDType* skipRefp() const { return (AstNodeDType*)this; }
     virtual AstNodeDType* skipRefToConstp() const { return (AstNodeDType*)this; }
     virtual AstNodeDType* skipRefToEnump() const { return (AstNodeDType*)this; }
+    virtual bool similarDType(AstNodeDType* samep) const { return this==samep; }
     virtual int widthAlignBytes() const { return 1; }
     virtual int widthTotalBytes() const { return 1; }
     string cellName() const { return m_cellName; }
@@ -540,6 +551,8 @@ public:
 	return (m_refDTypep==samep->castRefDType()->m_refDTypep
 		&& m_name==samep->castRefDType()->m_name
 		&& m_packagep==samep->castRefDType()->m_packagep); }
+    virtual bool similarDType(AstNodeDType* samep) const {
+	return skipRefp()->similarDType(samep->skipRefp()); }
     virtual V3Hash sameHash() const { return V3Hash(V3Hash(m_refDTypep),V3Hash(m_packagep)); }
     virtual void dump(ostream& str=cout);
     virtual string name() const { return m_name; }
@@ -623,6 +636,7 @@ public:
     void refDTypep(AstNodeDType* nodep) { m_refDTypep = nodep; }
     virtual AstNodeDType* virtRefDTypep() const { return m_refDTypep; }
     virtual void virtRefDTypep(AstNodeDType* nodep) { refDTypep(nodep); }
+    virtual bool similarDType(AstNodeDType* samep) const { return this==samep; }
     //
     virtual AstBasicDType* basicp() const { return subDTypep()->basicp(); }  // (Slow) recurse down to find basic data type (Note don't need virtual - AstVar isn't a NodeDType)
     AstNodeDType* dtypeSkipRefp() const { return subDTypep()->skipRefp(); }	// op1 = Range of variable (Note don't need virtual - AstVar isn't a NodeDType)
@@ -704,6 +718,7 @@ public:
 	m_refDTypep = m_refDTypep->clonep();
     }}
     virtual bool same(AstNode* samep) const { return m_uniqueNum==samep->castEnumDType()->m_uniqueNum; }
+    virtual bool similarDType(AstNodeDType* samep) const { return this==samep; }
     virtual V3Hash sameHash() const { return V3Hash(m_uniqueNum); }
     AstNodeDType* getChildDTypep() const { return childDTypep(); }
     AstNodeDType* childDTypep() const { return op1p()->castNodeDType(); } // op1 = Data type
@@ -733,6 +748,7 @@ public:
     ASTNODE_NODE_FUNCS(ParseTypeDType)
     AstNodeDType* dtypep() const { return NULL; }
     // METHODS
+    virtual bool similarDType(AstNodeDType* samep) const { return this==samep; }
     virtual AstBasicDType* basicp() const { return NULL; }
     virtual AstNodeDType* skipRefp() const { return NULL; }
     virtual AstNodeDType* skipRefToConstp() const { return (AstNodeDType*)this; }
@@ -2642,28 +2658,24 @@ public:
 class AstValuePlusArgs : public AstNodeMath {
     // Parents: expr
     // Child: variable to set.  If NULL then this is a $test$plusargs instead of $value$plusargs
-private:
-    string	m_text;
 public:
-    AstValuePlusArgs(FileLine* fileline, const string& text, AstNode* exprsp)
-	: AstNodeMath (fileline), m_text(text) {
-	setOp1p(exprsp);
+    AstValuePlusArgs(FileLine* fileline, AstNode* searchp, AstNode* outp)
+	: AstNodeMath (fileline) {
+	setOp1p(searchp); setOp2p(outp);
     }
     ASTNODE_NODE_FUNCS(ValuePlusArgs)
-    virtual string name()	const { return m_text; }
     virtual string verilogKwd() const { return "$value$plusargs"; }
-    virtual string emitVerilog() { return verilogKwd(); }
-    virtual string emitC() { return "VL_VALUEPLUSARGS_%nq(%lw, %P, NULL)"; }
+    virtual string emitVerilog() { return "%f$value$plusargs(%l, %k%r)"; }
+    virtual string emitC() { V3ERROR_NA; return ""; }
     virtual bool isGateOptimizable() const { return false; }
     virtual bool isPredictOptimizable() const { return false; }
     virtual bool cleanOut() { return true; }
-    virtual V3Hash sameHash() const { return V3Hash(text()); }
-    virtual bool same(AstNode* samep) const {
-	return text()==samep->castValuePlusArgs()->text(); }
-    AstNode*	exprsp()	const { return op1p(); }	// op1 = Expressions to output
-    void 	exprsp(AstNode* nodep)	{ setOp1p(nodep); }	// op1 = Expressions to output
-    string 	text()		const { return m_text; }	// * = Text to display
-    void 	text(const string& text) { m_text=text; }
+    virtual V3Hash sameHash() const { return V3Hash(); }
+    virtual bool same(AstNode* samep) const { return true; }
+    AstNode*	searchp() const { return op1p(); }	// op1 = Search expression
+    void 	searchp(AstNode* nodep)	{ setOp1p(nodep); }
+    AstNode*	outp() const { return op2p(); }		// op2 = Expressions to output
+    void 	outp(AstNode* nodep) { setOp2p(nodep); }
 };
 
 class AstTestPlusArgs : public AstNodeMath {
@@ -4657,6 +4669,7 @@ public:
 	dtypeSetLogicBool(); }
     ASTNODE_NODE_FUNCS(EqWild)
     virtual AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) { return new AstEqWild(this->fileline(), lhsp, rhsp); }
+    static AstNodeBiop* newTyped(FileLine* fl, AstNode* lhsp, AstNode* rhsp);  // Return AstEqWild/AstEqD
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opWildEq(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %f==? %r)"; }
     virtual string emitC() { return "VL_EQ_%lq(%lW, %P, %li, %ri)"; }

src/V3Broken.cpp

@@ -62,7 +62,7 @@ public:
 	if (debug()>=9) cout<<"-nodeDel:  "<<(void*)(nodep)<<endl;
 	NodeMap::iterator iter = s_nodes.find(nodep);
 	if (iter==s_nodes.end() || !(iter->second & FLAG_ALLOCATED)) {
-	    ((AstNode*)(nodep))->v3fatalSrc("Deleting AstNode object that was never tracked or already deleted\n");
+	    ((AstNode*)(nodep))->v3fatalSrc("Deleting AstNode object that was never tracked or already deleted");
 	}
 	if (iter!=s_nodes.end()) s_nodes.erase(iter);
     }
@@ -71,7 +71,7 @@ public:
 	if (debug()>=9) cout<<"-nodeNew:  "<<(void*)(nodep)<<endl;
 	NodeMap::iterator iter = s_nodes.find(nodep);
 	if (iter!=s_nodes.end() || (iter->second & FLAG_ALLOCATED)) {
-	    ((AstNode*)(nodep))->v3fatalSrc("Newing AstNode object that is already allocated\n");
+	    ((AstNode*)(nodep))->v3fatalSrc("Newing AstNode object that is already allocated");
 	}
 	if (iter == s_nodes.end()) {
 	    int flags = FLAG_ALLOCATED;  // This int needed to appease GCC 4.1.2
@@ -94,16 +94,16 @@ public:
 	NodeMap::iterator iter = s_nodes.find(nodep);
 	if (iter == s_nodes.end()) {
 #ifdef VL_LEAK_CHECKS
-	    nodep->v3fatalSrc("AstNode is in tree, but not allocated\n");
+	    nodep->v3fatalSrc("AstNode is in tree, but not allocated");
 #endif
 	} else {
 	    if (!(iter->second & FLAG_ALLOCATED)) {
 #ifdef VL_LEAK_CHECKS
-		nodep->v3fatalSrc("AstNode is in tree, but not allocated\n");
+		nodep->v3fatalSrc("AstNode is in tree, but not allocated");
 #endif
 	    }
 	    if (iter->second & FLAG_IN_TREE) {
-		nodep->v3fatalSrc("AstNode is already in tree at another location\n");
+		nodep->v3fatalSrc("AstNode is already in tree at another location");
 	    }
 	}
 	int or_flags = FLAG_IN_TREE | (linkable?FLAG_LINKABLE:0);

src/V3CCtors.cpp

@@ -75,7 +75,8 @@ public:
 	m_numStmts += 1;
     }
 
-    V3CCtorsVisitor(AstNodeModule* nodep, string basename, string argsp="", string callargsp="") {
+    V3CCtorsVisitor(AstNodeModule* nodep, string basename, string argsp="", string callargsp="",
+		    const string& stmt="") {
 	m_basename = basename;
 	m_argsp = argsp;
 	m_callargsp = callargsp;
@@ -87,6 +88,9 @@ public:
 	m_tlFuncp->isStatic(false);
 	m_tlFuncp->slow(true);
 	m_tlFuncp->argTypes(m_argsp);
+	if (stmt != "") {
+	    m_tlFuncp->addStmtsp(new AstCStmt(nodep->fileline(), stmt));
+	}
 	m_funcp = m_tlFuncp;
 	m_modp->addStmtp(m_tlFuncp);
     }
@@ -100,7 +104,8 @@ void V3CCtors::cctorsAll() {
 	// Process each module in turn
 	V3CCtorsVisitor var_reset (modp, "_ctor_var_reset");
 	V3CCtorsVisitor configure_coverage (modp, "_configure_coverage",
-						   EmitCBaseVisitor::symClassVar()+ ", bool first", "vlSymsp, first");
+					    EmitCBaseVisitor::symClassVar()+ ", bool first", "vlSymsp, first",
+					    "if (0 && vlSymsp && first) {} // Prevent unused\n");
 
 	for (AstNode* np = modp->stmtsp(); np; np = np->nextp()) {
 	    AstVar* varp = np->castVar();

src/V3Case.cpp

@@ -174,7 +174,7 @@ private:
 	    for (AstNode* icondp = itemp->condsp(); icondp!=NULL; icondp=icondp->nextp()) {
 		//if (debug()>=9) icondp->dumpTree(cout," caseitem: ");
 		AstConst* iconstp = icondp->castConst();
-		if (!iconstp) nodep->v3fatalSrc("above 'can't parse' should have caught this\n");
+		if (!iconstp) nodep->v3fatalSrc("above 'can't parse' should have caught this");
 		if (neverItem(nodep, iconstp)) {
 		    // X in casez can't ever be executed
 		} else {

src/V3Cdc.cpp

@@ -629,9 +629,9 @@ private:
     }
     virtual void visit(AstNodeVarRef* nodep) {
 	if (m_scopep) {
-	    if (!m_logicVertexp) nodep->v3fatalSrc("Var ref not under a logic block\n");
+	    if (!m_logicVertexp) nodep->v3fatalSrc("Var ref not under a logic block");
 	    AstVarScope* varscp = nodep->varScopep();
-	    if (!varscp) nodep->v3fatalSrc("Var didn't get varscoped in V3Scope.cpp\n");
+	    if (!varscp) nodep->v3fatalSrc("Var didn't get varscoped in V3Scope.cpp");
 	    CdcVarVertex* varvertexp = makeVarVertex(varscp);
 	    UINFO(5," VARREF to "<<varscp<<endl);
 	    // We use weight of one for normal edges,

src/V3Changed.cpp

@@ -253,7 +253,7 @@ private:
 	AstNode::user1ClearTree();
 	// Create the change detection function
 	AstScope* scopep = nodep->scopep();
-	if (!scopep) nodep->v3fatalSrc("No scope found on top level, perhaps you have no statements?\n");
+	if (!scopep) nodep->v3fatalSrc("No scope found on top level, perhaps you have no statements?");
 	m_statep->m_scopetopp = scopep;
 
 	// Create a wrapper change detection function that calls each change detection function

src/V3ClkGater.cpp

@@ -559,7 +559,7 @@ class GaterVisitor : public GaterBaseVisitor {
 		if (!vVxp->inBeginp()) {
 		    // At this point, any variable not linked is an error
 		    // (It should have at least landed under the Head node)
-		    vVxp->nodep()->v3fatalSrc("Variable became stranded in clk gate detection\n");
+		    vVxp->nodep()->v3fatalSrc("Variable became stranded in clk gate detection");
 		}
 		if (!lastVxp || vVxp->sortCmp(lastVxp)) {
 		    // Different sources for this new node

src/V3Clock.cpp

@@ -192,7 +192,7 @@ private:
 	UINFO(4," TOPSCOPE   "<<nodep<<endl);
 	m_topScopep=nodep;
 	m_scopep = nodep->scopep();
-	if (!m_scopep) nodep->v3fatalSrc("No scope found on top level, perhaps you have no statements?\n");
+	if (!m_scopep) nodep->v3fatalSrc("No scope found on top level, perhaps you have no statements?");
 	//VV*****  We reset all user1p()
 	AstNode::user1ClearTree();
 	// Make top functions

src/V3Combine.cpp

@@ -239,7 +239,7 @@ private:
 	    V3Hash hashval = it->first;
 	    AstNode* node1p = it->second;
 	    if (!node1p->castCFunc()) continue;
-	    if (hashval.isIllegal()) node1p->v3fatalSrc("Illegal (unhashed) nodes\n");
+	    if (hashval.isIllegal()) node1p->v3fatalSrc("Illegal (unhashed) nodes");
 	    for (V3Hashed::iterator eqit = it; eqit != m_hashed.end(); ++eqit) {
 		AstNode* node2p = eqit->second;
 		if (!(eqit->first == hashval)) break;

src/V3Const.cpp

@@ -555,7 +555,7 @@ private:
 	// Replace oldp node with a constant set to specified value
 	UASSERT (oldp, "Null old\n");
 	if (oldp->castConst() && !oldp->castConst()->num().isFourState()) {
-	    oldp->v3fatalSrc("Already constant??\n");
+	    oldp->v3fatalSrc("Already constant??");
 	}
 	AstNode* newp = new AstConst(oldp->fileline(), num);
 	newp->dtypeFrom(oldp);
@@ -1491,6 +1491,14 @@ private:
 			did=true;
 		    }
 		}
+		else if (m_params && valuep->castInitArray() && nodep->backp()->castPin()) {
+		    // Allow parameters to pass arrays
+		    // Earlier recursion of InitArray made sure each array value is constant
+		    // This exception is fairly fragile, i.e. doesn't support arrays of arrays or other stuff
+		    AstNode* newp = valuep->cloneTree(false);
+		    nodep->replaceWith(newp); nodep->deleteTree(); VL_DANGLING(nodep);
+		    did = true;
+		}
 	    }
 	}
 	if (!did && m_required) {

src/V3Delayed.cpp

@@ -207,8 +207,8 @@ private:
 	    dimvalp.push_front(valp);
 	}
 	AstVarRef* varrefp = dimselp->castVarRef();
-	if (!varrefp) nodep->v3fatalSrc("No var underneath arraysels\n");
-	if (!varrefp->varScopep()) varrefp->v3fatalSrc("Var didn't get varscoped in V3Scope.cpp\n");
+	if (!varrefp) nodep->v3fatalSrc("No var underneath arraysels");
+	if (!varrefp->varScopep()) varrefp->v3fatalSrc("Var didn't get varscoped in V3Scope.cpp");
 	varrefp->unlinkFrBack();
 	AstVar* oldvarp = varrefp->varp();
 	int modVecNum = oldvarp->user4();  oldvarp->user4(modVecNum+1);
@@ -393,7 +393,7 @@ private:
 		if (!m_activep) nodep->v3fatalSrc("<= not under sensitivity block");
 		if (!m_activep->hasClocked()) nodep->v3error("Internal: Blocking <= assignment in non-clocked block, should have converted in V3Active");
 		AstVarScope* oldvscp = nodep->varScopep();
-		if (!oldvscp) nodep->v3fatalSrc("Var didn't get varscoped in V3Scope.cpp\n");
+		if (!oldvscp) nodep->v3fatalSrc("Var didn't get varscoped in V3Scope.cpp");
 		AstVarScope* dlyvscp = oldvscp->user1p()->castVarScope();
 		if (dlyvscp) {  // Multiple use of delayed variable
 		    AstActive* oldactivep = dlyvscp->user2p()->castActive();
@@ -433,7 +433,7 @@ private:
     }
 
     virtual void visit(AstNodeFor* nodep) {
-	nodep->v3fatalSrc("For statements should have been converted to while statements in V3Begin\n");
+	nodep->v3fatalSrc("For statements should have been converted to while statements in V3Begin");
     }
     virtual void visit(AstWhile* nodep) {
 	bool oldloop = m_inLoop;

src/V3EmitC.cpp

@@ -217,7 +217,7 @@ public:
     }
     virtual void visit(AstNodeCase* nodep) {
 	// In V3Case...
-	nodep->v3fatalSrc("Case statements should have been reduced out\n");
+	nodep->v3fatalSrc("Case statements should have been reduced out");
     }
     virtual void visit(AstComment* nodep) {
 	putsDecoration((string)"// "+nodep->name()+" at "+nodep->fileline()->ascii()+"\n");
@@ -277,54 +277,15 @@ public:
 	displayNode(nodep, NULL, nodep->text(), nodep->exprsp(), true);
     }
     virtual void visit(AstValuePlusArgs* nodep) {
-	string prefix;
-	char format = '?';
-	bool pct=false;
-	int got=0;
-	string txt = nodep->text();
-	for (string::const_iterator it=txt.begin(); it!=txt.end(); ++it) {
-	    char ch = *it;
-	    if (pct) {
-		pct = false;
-		switch (tolower(ch)) {
-		case '%':
-		    prefix += ch;
-		    break;
-		case 'd': // FALLTHRU
-		case 'o': // FALLTHRU
-		case 'h': // FALLTHRU
-		case 'x': // FALLTHRU
-		case 'b': // FALLTHRU
-		case 'v': // FALLTHRU
-		case 's':
-		    got++; format = tolower(ch);
-		    break;
-		case 'e': // FALLTHRU
-		case 'f': // FALLTHRU
-		case 'g':
-		    got++; format = tolower(ch);
-		    nodep->v3error("Unsupported $value$plusargs format qualifier: '"<<ch<<"'"<<endl);
-		    break;
-		default:
-		    got++;
-		    nodep->v3error("Illegal $value$plusargs format qualifier: '"<<ch<<"'"<<endl);
-		    break;
-		}
-	    }
-	    else if (ch == '%') pct = true;
-	    else prefix += ch;
-	}
-	if (got!=1) nodep->v3error("Missing or extra $value$plusargs format qualifier: '"<<nodep->text()<<"'"<<endl);
-	puts("VL_VALUEPLUSARGS_I");
-	emitIQW(nodep->exprsp());
+	puts("VL_VALUEPLUSARGS_IN");
+	emitIQW(nodep->outp());
 	puts("(");
-	puts(cvtToStr(nodep->exprsp()->widthMin()));  // Note argument width, not node width (which is always 32)
-	putbs(",");
-	putsQuoted(prefix);
-	putbs(",");
-	puts("'"); puts(cvtToStr(format)); puts("'");
+	puts(cvtToStr(nodep->outp()->widthMin()));
 	puts(",");
-	nodep->exprsp()->iterateAndNext(*this);
+	emitCvtPackStr(nodep->searchp());
+	puts(",");
+	putbs("");
+	nodep->outp()->iterateAndNext(*this);
 	puts(")");
     }
     virtual void visit(AstTestPlusArgs* nodep) {
@@ -548,6 +509,30 @@ public:
 	}
 	visit(nodep->castNodeBiop());
     }
+    virtual void visit(AstPow* nodep) {
+	if (nodep->widthWords() > VL_MULS_MAX_WORDS) {
+	    nodep->v3error("Unsupported: Power of "<<nodep->width()<<" bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h");
+	}
+	visit(nodep->castNodeBiop());
+    }
+    virtual void visit(AstPowSS* nodep) {
+	if (nodep->widthWords() > VL_MULS_MAX_WORDS) {
+	    nodep->v3error("Unsupported: Power of "<<nodep->width()<<" bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h");
+	}
+	visit(nodep->castNodeBiop());
+    }
+    virtual void visit(AstPowSU* nodep) {
+	if (nodep->widthWords() > VL_MULS_MAX_WORDS) {
+	    nodep->v3error("Unsupported: Power of "<<nodep->width()<<" bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h");
+	}
+	visit(nodep->castNodeBiop());
+    }
+    virtual void visit(AstPowUS* nodep) {
+	if (nodep->widthWords() > VL_MULS_MAX_WORDS) {
+	    nodep->v3error("Unsupported: Power of "<<nodep->width()<<" bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h");
+	}
+	visit(nodep->castNodeBiop());
+    }
     virtual void visit(AstCCast* nodep) {
 	// Extending a value of the same word width is just a NOP.
 	if (nodep->size()>VL_WORDSIZE) {
@@ -618,6 +603,23 @@ public:
 	puts(nodep->hiername());
 	puts(nodep->varp()->name());
     }
+    void emitCvtPackStr(AstNode* nodep) { 
+	if (AstConst* constp = nodep->castConst()) {
+	    putbs("string(");
+	    putsQuoted(constp->num().toString());
+	    puts(")");
+	} else {
+	    putbs("VL_CVT_PACK_STR_N");
+	    emitIQW(nodep);
+	    puts("(");
+	    if (nodep->isWide()) {
+		puts(cvtToStr(nodep->widthWords()));  // Note argument width, not node width (which is always 32)
+		puts(",");
+	    }
+	    nodep->iterateAndNext(*this);
+	    puts(")");
+	}
+    }
     void emitConstant(AstConst* nodep, AstVarRef* assigntop, const string& assignString) {
 	// Put out constant set to the specified variable, or given variable in a string
 	if (nodep->num().isFourState()) {

src/V3EmitV.cpp

@@ -238,10 +238,6 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
     virtual void visit(AstSFormatF* nodep) {
 	visitNodeDisplay(nodep, NULL, nodep->text(), nodep->exprsp());
     }
-    virtual void visit(AstValuePlusArgs* nodep) {
-	visitNodeDisplay(nodep, NULL, nodep->text(), nodep->exprsp());
-    }
-
     virtual void visit(AstFOpen* nodep) {
 	putfs(nodep,nodep->verilogKwd());
 	putbs(" (");

src/V3FileLine.cpp

@@ -270,7 +270,7 @@ void FileLine::operator delete(void* objp, size_t size) {
     if (it != fileLineLeakChecks.end()) {
 	fileLineLeakChecks.erase(it);
     } else {
-	flp->v3fatalSrc("Deleting FileLine object that was never tracked\n");
+	flp->v3fatalSrc("Deleting FileLine object that was never tracked");
     }
     ::operator delete(objp);
 }

src/V3Gate.cpp

@@ -113,6 +113,20 @@ public:
 	}
 	return ret;
     }
+    // Returns only the result from the LAST vertex iterated over
+    // Note: This behaves differently than iterateInEdges() in that it will traverse
+    //		all edges that exist when it is initially called, whereas
+    //		iterateInEdges() will stop traversing edges if one is deleted
+    VNUser iterateCurrentOutEdges(GateGraphBaseVisitor& v, VNUser vu=VNUser(0)) {
+	VNUser ret = VNUser(0);
+	V3GraphEdge* next_edgep = NULL;
+	for (V3GraphEdge* edgep = outBeginp(); edgep; edgep = next_edgep) {
+	    // Need to find the next edge before visiting in case the edge is deleted
+	    next_edgep = edgep->outNextp();
+	    ret = dynamic_cast<GateEitherVertex*>(edgep->top())->accept(v, vu);
+	}
+	return ret;
+    }
 };
 
 class GateVarVertex : public GateEitherVertex {
@@ -291,6 +305,7 @@ private:
     // {statement}Node::user1p	-> GateLogicVertex* for this statement
     // AstVarScope::user2	-> bool: Signal used in SenItem in *this* always statement
     // AstVar::user2		-> bool: Warned about SYNCASYNCNET
+    // AstVarNodeRef::user2	-> bool: ConcatOffset visited
     AstUser1InUse	m_inuser1;
     AstUser2InUse	m_inuser2;
 
@@ -358,6 +373,7 @@ private:
     void replaceAssigns();
     void dedupe();
     void mergeAssigns();
+    void decomposeClkVectors();
 
     // VISITORS
     virtual void visit(AstNetlist* nodep) {
@@ -365,6 +381,8 @@ private:
 	//if (debug()>6) m_graph.dump();
 	if (debug()>6) m_graph.dumpDotFilePrefixed("gate_pre");
 	warnSignals();  // Before loss of sync/async pointers
+	// Decompose clock vectors -- need to do this before removing redundant edges
+	decomposeClkVectors();
 	m_graph.removeRedundantEdgesSum(&V3GraphEdge::followAlwaysTrue);
 	m_graph.dumpDotFilePrefixed("gate_simp");
 	// Find gate interconnect and optimize
@@ -409,9 +427,9 @@ private:
     }
     virtual void visit(AstNodeVarRef* nodep) {
 	if (m_scopep) {
-	    if (!m_logicVertexp) nodep->v3fatalSrc("Var ref not under a logic block\n");
+	    if (!m_logicVertexp) nodep->v3fatalSrc("Var ref not under a logic block");
 	    AstVarScope* varscp = nodep->varScopep();
-	    if (!varscp) nodep->v3fatalSrc("Var didn't get varscoped in V3Scope.cpp\n");
+	    if (!varscp) nodep->v3fatalSrc("Var didn't get varscoped in V3Scope.cpp");
 	    GateVarVertex* vvertexp = makeVarVertex(varscp);
 	    UINFO(5," VARREF to "<<varscp<<endl);
 	    if (m_inSenItem) vvertexp->setIsClock();
@@ -484,7 +502,7 @@ private:
     }
     virtual void visit(AstConcat* nodep) {
 	if (nodep->backp()->castNodeAssign() && nodep->backp()->castNodeAssign()->lhsp()==nodep) {
-	    nodep->v3fatalSrc("Concat on LHS of assignment; V3Const should have deleted it\n");
+	    nodep->v3fatalSrc("Concat on LHS of assignment; V3Const should have deleted it");
 	}
 	nodep->iterateChildren(*this);
     }
@@ -704,7 +722,7 @@ void GateVisitor::replaceAssigns() {
 		if (!vscp->valuep()->castNodeMath()
 		    || vscp->valuep()->nextp()) {
 		    vscp->dumpTree(cerr, "vscStrange: ");
-		    vscp->v3fatalSrc("Value of varscope not mathematical\n");
+		    vscp->v3fatalSrc("Value of varscope not mathematical");
 		}
 	    }
 	}
@@ -1238,6 +1256,200 @@ void GateVisitor::mergeAssigns() {
     m_statAssignMerged += merger.numMergedAssigns();
 }
 
+//######################################################################
+// Find a var's offset in a concatenation
+
+class GateConcatVisitor : public GateBaseVisitor {
+private:
+    // STATE
+    AstVarScope*	m_vscp;		// Varscope we're trying to find
+    int			m_offset;	// Current offset of varscope
+    int			m_found_offset;	// Found offset of varscope
+    bool		m_found;	// Offset found
+
+    // VISITORS
+    virtual void visit(AstNodeVarRef* nodep) {
+	UINFO(9,"CLK DECOMP Concat search var (off = "<<m_offset<<") - "<<nodep<<endl);
+	if (nodep->varScopep() == m_vscp && !nodep->user2() && !m_found) {
+	    // A concatenation may use the same var multiple times
+	    // But the graph will initially have an edge per instance
+	    nodep->user2(true);
+	    m_found_offset = m_offset;
+	    m_found = true;
+	    UINFO(9,"CLK DECOMP Concat found var (off = "<<m_offset<<") - "<<nodep<<endl);
+	}
+	m_offset += nodep->dtypep()->width();
+    }
+    virtual void visit(AstConcat* nodep) {
+	UINFO(9,"CLK DECOMP Concat search (off = "<<m_offset<<") - "<<nodep<<endl);
+	nodep->rhsp()->iterate(*this);
+	nodep->lhsp()->iterate(*this);
+    }
+    //--------------------
+    // Default
+    virtual void visit(AstNode* nodep) {
+	nodep->iterateChildren(*this);
+    }
+public:
+    // CONSTUCTORS
+    GateConcatVisitor() {
+	m_vscp = NULL;
+	m_offset = 0;
+	m_found_offset = 0;
+	m_found = false;
+    }
+    virtual ~GateConcatVisitor() {}
+    // PUBLIC METHODS
+    bool concatOffset(AstConcat* concatp, AstVarScope* vscp, int& offsetr) {
+	m_vscp = vscp;
+	m_offset = 0;
+	m_found = false;
+	// Iterate
+	concatp->accept(*this);
+	UINFO(9,"CLK DECOMP Concat Offset (found = "<<m_found<<") ("<<m_found_offset<<") - "<<concatp<<" : "<<vscp<<endl);
+	offsetr = m_found_offset;
+	return m_found;
+    }
+};
+
+//######################################################################
+// Recurse through the graph, looking for clock vectors to bypass
+
+class GateClkDecompState {
+public:
+    int				m_offset;
+    AstVarScope*		m_last_vsp;
+    GateClkDecompState(int offset, AstVarScope* vsp) {
+	m_offset = offset;
+	m_last_vsp = vsp;
+    }
+    virtual ~GateClkDecompState() {}
+};
+
+class GateClkDecompGraphVisitor : public GateGraphBaseVisitor {
+private:
+    // NODE STATE
+    // AstVarScope::user2p	-> bool: already visited
+    V3Graph*			m_graphp;
+    int				m_seen_clk_vectors;
+    AstVarScope*		m_clk_vsp;
+    GateVarVertex*		m_clk_vvertexp;
+    GateConcatVisitor		m_concat_visitor;
+    int				m_total_seen_clk_vectors;
+    int				m_total_decomposed_clk_vectors;
+
+    virtual VNUser visit(GateVarVertex* vvertexp, VNUser vu) {
+	// Check that we haven't been here before
+	AstVarScope* vsp = vvertexp->varScp();
+	if (vsp->user2SetOnce()) return VNUser(0);
+	UINFO(9,"CLK DECOMP Var - "<<vvertexp<<" : "<<vsp<<endl);
+	if (vsp->varp()->width() > 1) {
+	    m_seen_clk_vectors++;
+	    m_total_seen_clk_vectors++;
+	}
+	GateClkDecompState* currState = (GateClkDecompState*) vu.c();
+	GateClkDecompState nextState(currState->m_offset, vsp);
+	vvertexp->iterateCurrentOutEdges(*this, VNUser(&nextState));
+	if (vsp->varp()->width() > 1) {
+	    m_seen_clk_vectors--;
+	}
+	vsp->user2(false);
+	return VNUser(0);
+    }
+
+    virtual VNUser visit(GateLogicVertex* lvertexp, VNUser vu) {
+	GateClkDecompState* currState = (GateClkDecompState*) vu.c();
+	int clk_offset = currState->m_offset;
+	if (AstAssignW* assignp = lvertexp->nodep()->castAssignW()) {
+	    UINFO(9,"CLK DECOMP Logic (off = "<<clk_offset<<") - "<<lvertexp<<" : "<<m_clk_vsp<<endl);
+	    if (AstSel* rselp = assignp->rhsp()->castSel()) {
+		if (rselp->lsbp()->castConst() && rselp->widthp()->castConst()) {
+		    if (clk_offset < rselp->lsbConst() || clk_offset > rselp->msbConst()) {
+			UINFO(9,"CLK DECOMP Sel [ "<<rselp->msbConst()<<" : "<<rselp->lsbConst()<<" ] dropped clock ("<<clk_offset<<")"<<endl);
+			return VNUser(0);
+		    }
+		    clk_offset -= rselp->lsbConst();
+		} else {
+		    return VNUser(0);
+		}
+	    } else if (AstConcat* catp = assignp->rhsp()->castConcat()) {
+		UINFO(9,"CLK DECOMP Concat searching - "<<assignp->lhsp()<<endl);
+		int concat_offset;
+		if (!m_concat_visitor.concatOffset(catp, currState->m_last_vsp, concat_offset)) {
+		    return VNUser(0);
+		}
+		clk_offset += concat_offset;
+	    }
+	    if (AstSel* lselp = assignp->lhsp()->castSel()) {
+		if (lselp->lsbp()->castConst() && lselp->widthp()->castConst()) {
+		    clk_offset += lselp->lsbConst();
+		} else {
+		    return VNUser(0);
+		}
+	    } else if (AstVarRef* vrp = assignp->lhsp()->castVarRef()) {
+		if (vrp->dtypep()->width() == 1 && m_seen_clk_vectors) {
+		    if (clk_offset != 0) {
+			UINFO(9,"Should only make it here with clk_offset = 0"<<endl);
+			return VNUser(0);
+		    }
+		    UINFO(9,"CLK DECOMP Connecting - "<<assignp->lhsp()<<" <-> "<<m_clk_vsp<<endl);
+		    AstNode* rhsp = assignp->rhsp();
+		    rhsp->replaceWith(new AstVarRef(rhsp->fileline(), m_clk_vsp, false));
+		    for (V3GraphEdge* edgep = lvertexp->inBeginp(); edgep; ) {
+			edgep->unlinkDelete(); VL_DANGLING(edgep);
+		    }
+		    new V3GraphEdge(m_graphp, m_clk_vvertexp, lvertexp, 1);
+		    m_total_decomposed_clk_vectors++;
+		}
+	    }
+	    GateClkDecompState nextState(clk_offset, currState->m_last_vsp);
+	    return lvertexp->iterateCurrentOutEdges(*this, VNUser(&nextState));
+	}
+	return VNUser(0);
+    }
+
+public:
+    GateClkDecompGraphVisitor(V3Graph* graphp) {
+	m_graphp = graphp;
+	m_seen_clk_vectors = 0;
+	m_clk_vsp = NULL;
+	m_clk_vvertexp = NULL;
+	m_total_seen_clk_vectors = 0;
+	m_total_decomposed_clk_vectors = 0;
+    }
+    virtual ~GateClkDecompGraphVisitor() {
+	V3Stats::addStat("Optimizations, Clocker seen vectors", m_total_seen_clk_vectors);
+	V3Stats::addStat("Optimizations, Clocker decomposed vectors", m_total_decomposed_clk_vectors);
+    }
+    void clkDecomp(GateVarVertex* vvertexp) {
+	UINFO(9,"CLK DECOMP Starting Var - "<<vvertexp<<endl);
+	m_seen_clk_vectors = 0;
+	m_clk_vsp = vvertexp->varScp();
+	m_clk_vvertexp = vvertexp;
+	GateClkDecompState nextState(0, m_clk_vsp);
+	vvertexp->accept(*this, VNUser(&nextState));
+    }
+};
+
+void GateVisitor::decomposeClkVectors() {
+    UINFO(9,"Starting clock decomposition"<<endl);
+    AstNode::user2ClearTree();
+    GateClkDecompGraphVisitor decomposer(&m_graph);
+    for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp=itp->verticesNextp()) {
+	if (GateVarVertex* vertp = dynamic_cast<GateVarVertex*>(itp)) {
+	    AstVarScope* vsp = vertp->varScp();
+	    if (vsp->varp()->attrClocker() == AstVarAttrClocker::CLOCKER_YES) {
+		if (vsp->varp()->width() > 1) {
+		    UINFO(9,"Clocker > 1 bit, not decomposing: "<<vsp<<endl);
+		} else {
+		    UINFO(9,"CLK DECOMP - "<<vertp<<" : "<<vsp<<endl);
+		    decomposer.clkDecomp(vertp);
+		}
+	    }
+	}
+    }
+}
+
 
 //######################################################################
 // Convert VARSCOPE(ASSIGN(default, VARREF)) to just VARSCOPE(default)

src/V3GraphAlg.cpp

@@ -529,7 +529,7 @@ double V3Graph::orderDFSIterate(V3GraphVertex* vertexp) {
     // Compute fanouts of each node
     // If forward edge, don't double count that fanout
     if (vertexp->user() == 2) return vertexp->fanout();  // Already processed it
-    if (vertexp->user() == 1) v3fatalSrc("Loop found, backward edges should be dead\n");
+    if (vertexp->user() == 1) v3fatalSrc("Loop found, backward edges should be dead");
     vertexp->user(1);
     double fanout = 0;
     for (V3GraphEdge* edgep = vertexp->outBeginp(); edgep; edgep = edgep->outNextp()) {

src/V3GraphDfa.cpp

@@ -44,7 +44,7 @@ DfaVertex* DfaGraph::findStart() {
 		startp = vvertexp;
 	    }
 	} else {
-	    v3fatalSrc("Non DfaVertex in DfaGraph\n");
+	    v3fatalSrc("Non DfaVertex in DfaGraph");
 	}
     }
     if (!startp) v3fatalSrc("No start point in NFA graph");
@@ -520,7 +520,7 @@ private:
 		}
 	    }
 	}
-	if (!acceptp) v3fatalSrc("No accepting vertex in DFA\n");
+	if (!acceptp) v3fatalSrc("No accepting vertex in DFA");
 
 	// Remap edges
 	for (V3GraphVertex* vertexp = m_graphp->verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {

src/V3Inline.cpp

@@ -277,7 +277,7 @@ private:
 	    AstVarRef* exprvarrefp = nodep->user2p()->castVarRef();
 	    UINFO(8,"connectto: "<<nodep->user2p()<<endl);
 	    if (!exprconstp && !exprvarrefp) {
-		nodep->v3fatalSrc("Unknown interconnect type; pinReconnectSimple should have cleared up\n");
+		nodep->v3fatalSrc("Unknown interconnect type; pinReconnectSimple should have cleared up");
 	    }
 	    if (exprconstp) {
 		m_modp->addStmtp(new AstAssignW(nodep->fileline(),
@@ -362,7 +362,7 @@ private:
 		nodep->varp( exprvarrefp->varp() );
 	    }
 	    else {
-		nodep->v3fatalSrc("Null connection?\n");
+		nodep->v3fatalSrc("Null connection?");
 	    }
 	}
 	nodep->name(nodep->varp()->name());
@@ -514,7 +514,7 @@ private:
 
 		AstNode* connectRefp = pinp->exprp();
 		if (!connectRefp->castConst() && !connectRefp->castVarRef()) {
-		    pinp->v3fatalSrc("Unknown interconnect type; pinReconnectSimple should have cleared up\n");
+		    pinp->v3fatalSrc("Unknown interconnect type; pinReconnectSimple should have cleared up");
 		}
 		if (pinNewVarp->isOutOnly() && connectRefp->castConst()) {
 		    pinp->v3error("Output port is connected to a constant pin, electrical short");

src/V3Inst.cpp

@@ -90,7 +90,7 @@ private:
 	    // Make a ASSIGNW (expr, pin)
 	    AstNode*  exprp  = nodep->exprp()->cloneTree(false);
 	    if (exprp->width() != nodep->modVarp()->width())
-		nodep->v3fatalSrc("Width mismatch, should have been handled in pinReconnectSimple\n");
+		nodep->v3fatalSrc("Width mismatch, should have been handled in pinReconnectSimple");
 	    if (nodep->modVarp()->isInout()) {
 		nodep->v3fatalSrc("Unsupported: Verilator is a 2-state simulator");
 	    } else if (nodep->modVarp()->isOutput()) {
@@ -154,14 +154,10 @@ public:
 
 //######################################################################
 
-class InstDeVisitor : public AstNVisitor {
-    // Find all cells with arrays, and convert to non-arrayed
+class InstDeModVarVisitor : public AstNVisitor {
+    // Expand all module variables, and save names for later reference
 private:
     // STATE
-    AstRange*	m_cellRangep;	// Range for arrayed instantiations, NULL for normal instantiations
-    int		m_instNum;	// Current instantiation number
-    int		m_instLsb;	// Current instantiation number
-
     typedef map<string,AstVar*> VarNameMap;
     VarNameMap	m_modVarNameMap;	// Per module, name of cloned variables
 
@@ -172,15 +168,109 @@ private:
     }
 
     // VISITORS
-    virtual void visit(AstNodeModule* nodep) {
+    virtual void visit(AstVar* nodep) {
+	if (nodep->dtypep()->castIfaceRefDType()) {
+	    UINFO(8,"   dm-1-VAR    "<<nodep<<endl);
+	    insert(nodep);
+	}
+	nodep->iterateChildren(*this);
+    }
+    // Save some time
+    virtual void visit(AstNodeMath*) {}
+    // Default: Just iterate
+    virtual void visit(AstNode* nodep) {
+	nodep->iterateChildren(*this);
+    }
+public:
+    // METHODS
+    void insert(AstVar* nodep) {
+	UINFO(8,"    dmINSERT    "<<nodep<<endl);
+	m_modVarNameMap.insert(make_pair(nodep->name(), nodep));
+    }
+    AstVar* find(const string& name) {
+	VarNameMap::iterator it = m_modVarNameMap.find(name);
+	if (it != m_modVarNameMap.end()) {
+	    return it->second;
+	} else {
+	    return NULL;
+	}
+    }
+    void dump() {
+	for (VarNameMap::iterator it=m_modVarNameMap.begin(); it!=m_modVarNameMap.end(); ++it) {
+	    cout<<"-namemap: "<<it->first<<" -> "<<it->second<<endl;
+	}
+    }
+public:
+    // CONSTUCTORS
+    explicit InstDeModVarVisitor() {}
+    void accept(AstNodeModule* nodep) {
+	UINFO(8,"  dmMODULE    "<<nodep<<endl);
 	m_modVarNameMap.clear();
+	nodep->accept(*this);
+    }
+    virtual ~InstDeModVarVisitor() {}
+};
+
+//######################################################################
+
+class InstDeVisitor : public AstNVisitor {
+    // Find all cells with arrays, and convert to non-arrayed
+private:
+    // STATE
+    AstRange*	m_cellRangep;	// Range for arrayed instantiations, NULL for normal instantiations
+    int		m_instNum;	// Current instantiation number
+    int		m_instLsb;	// Current instantiation number
+    InstDeModVarVisitor  m_deModVars;	// State of variables for current cell module
+
+    typedef map<string,AstVar*> VarNameMap;
+
+    static int debug() {
+	static int level = -1;
+	if (VL_UNLIKELY(level < 0)) level = v3Global.opt.debugSrcLevel(__FILE__);
+	return level;
+    }
+
+    // VISITORS
+    virtual void visit(AstVar* nodep) {
+	if (nodep->dtypep()->castUnpackArrayDType()
+	    && nodep->dtypep()->castUnpackArrayDType()->subDTypep()->castIfaceRefDType()) {
+	    UINFO(8,"   dv-vec-VAR    "<<nodep<<endl);
+	    AstUnpackArrayDType* arrdtype = nodep->dtypep()->castUnpackArrayDType();
+	    AstNode* prevp = NULL;
+	    for (int i = arrdtype->lsb(); i <= arrdtype->msb(); ++i) {
+		string varNewName = nodep->name() + "__BRA__" + cvtToStr(i) + "__KET__";
+		UINFO(8,"VAR name insert "<<varNewName<<"  "<<nodep<<endl);
+		if (!m_deModVars.find(varNewName)) {
+		    AstIfaceRefDType* ifaceRefp = arrdtype->subDTypep()->castIfaceRefDType()->cloneTree(false);
+		    arrdtype->addNextHere(ifaceRefp);
+		    ifaceRefp->cellp(NULL);
+
+		    AstVar* varNewp = nodep->cloneTree(false);
+		    varNewp->name(varNewName);
+		    varNewp->origName(varNewp->origName() + "__BRA__" + cvtToStr(i) + "__KET__");
+		    varNewp->dtypep(ifaceRefp);
+		    m_deModVars.insert(varNewp);
+		    if (!prevp) {
+			prevp = varNewp;
+		    } else {
+			prevp->addNextHere(varNewp);
+		    }
+		}
+	    }
+	    if (prevp) nodep->addNextHere(prevp);
+	    if (prevp && debug()==9) { prevp->dumpTree(cout, "newintf: "); cout << endl; }
+	}
 	nodep->iterateChildren(*this);
     }
 
     virtual void visit(AstCell* nodep) {
+	UINFO(4,"  CELL   "<<nodep<<endl);
+	// Find submodule vars
+	if (!nodep->modp()) nodep->v3fatalSrc("Unlinked");
+	m_deModVars.accept(nodep->modp());
+	//
 	if (nodep->rangep()) {
 	    m_cellRangep = nodep->rangep();
-	    UINFO(4,"  CELL   "<<nodep<<endl);
 
 	    AstVar* ifaceVarp = nodep->nextp()->castVar();
 	    bool isIface = ifaceVarp
@@ -199,9 +289,10 @@ private:
 		// The spec says we add [x], but that won't work in C...
 		newp->name(newp->name()+"__BRA__"+cvtToStr(m_instNum)+"__KET__");
 		newp->origName(newp->origName()+"__BRA__"+cvtToStr(m_instNum)+"__KET__");
+		UINFO(8,"    CELL loop  "<<newp<<endl);
 
-		// If this AstCell is actually an interface instantiation, let's ensure we also clone
-		// the IfaceRef.
+		// If this AstCell is actually an interface instantiation, also clone the IfaceRef
+		// within the same parent module as the cell
 		if (isIface) {
 		    AstUnpackArrayDType* arrdtype = ifaceVarp->dtypep()->castUnpackArrayDType();
 		    AstIfaceRefDType* origIfaceRefp = arrdtype->subDTypep()->castIfaceRefDType();
@@ -229,42 +320,11 @@ private:
 	    }
 	    nodep->unlinkFrBack(); pushDeletep(nodep); VL_DANGLING(nodep);
 	} else {
+	    m_cellRangep = NULL;
 	    nodep->iterateChildren(*this);
 	}
     }
 
-    virtual void visit(AstVar* nodep) {
-	bool isIface = nodep->dtypep()->castUnpackArrayDType()
-	    && nodep->dtypep()->castUnpackArrayDType()->subDTypep()->castIfaceRefDType();
-	if (isIface) {
-	    AstUnpackArrayDType* arrdtype = nodep->dtypep()->castUnpackArrayDType();
-	    AstNode* prev = NULL;
-	    for (int i = arrdtype->lsb(); i <= arrdtype->msb(); ++i) {
-		AstIfaceRefDType* ifaceRefp = arrdtype->subDTypep()->castIfaceRefDType()->cloneTree(false);
-		arrdtype->addNextHere(ifaceRefp);
-		ifaceRefp->cellp(NULL);
-
-		string varNewName = nodep->name() + "__BRA__" + cvtToStr(i) + "__KET__";
-		VarNameMap::iterator it = m_modVarNameMap.find(varNewName);
-		if (it == m_modVarNameMap.end()) {
-		    AstVar* varNewp = nodep->cloneTree(false);
-		    m_modVarNameMap.insert(make_pair(varNewName, varNewp));
-		    varNewp->name(varNewName);
-		    varNewp->origName(varNewp->origName() + "__BRA__" + cvtToStr(i) + "__KET__");
-		    varNewp->dtypep(ifaceRefp);
-		    if (!prev) {
-			prev = varNewp;
-		    } else {
-			prev->addNextHere(varNewp);
-		    }
-		}
-	    }
-	    if (prev) nodep->addNextHere(prev);
-	    if (prev && debug()==9) { prev->dumpTree(cout, "newintf: "); cout << endl; }
-	}
-	nodep->iterateChildren(*this);
-    }
-
     virtual void visit(AstPin* nodep) {
 	// Any non-direct pins need reconnection with a part-select
 	if (!nodep->exprp()) return; // No-connect
@@ -334,30 +394,28 @@ private:
 	    // Clone pin varp:
 	    for (int i = pinArrp->lsb(); i <= pinArrp->msb(); ++i) {
 		string varNewName = pinVarp->name() + "__BRA__" + cvtToStr(i) + "__KET__";
-		VarNameMap::iterator it = m_modVarNameMap.find(varNewName);
 		AstVar* varNewp = NULL;
 
-		// Only clone the var once for each module
+		// Only clone the var once for all usages of a given child module
 		if (!pinVarp->backp()) {
-		    if (it != m_modVarNameMap.end()) {
-			varNewp = it->second;
-		    }
+		    varNewp = m_deModVars.find(varNewName);
 		} else {
 		    AstIfaceRefDType* ifaceRefp = pinArrp->subDTypep()->castIfaceRefDType();
 		    ifaceRefp->cellp(NULL);
 		    varNewp = pinVarp->cloneTree(false);
-		    m_modVarNameMap.insert(make_pair(varNewName, varNewp));
 		    varNewp->name(varNewName);
 		    varNewp->origName(varNewp->origName() + "__BRA__" + cvtToStr(i) + "__KET__");
 		    varNewp->dtypep(ifaceRefp);
+		    m_deModVars.insert(varNewp);
 		    if (!prevp) {
 			prevp = varNewp;
 		    } else {
 			prevp->addNextHere(varNewp);
 		    }
 		}
-		if (varNewp == NULL) {
-		    nodep->v3fatalSrc("Module dearray failed\n");
+		if (!varNewp) {
+		    if (debug()>=9) m_deModVars.dump();
+		    nodep->v3fatalSrc("Module dearray failed for "<<AstNode::prettyName(varNewName));
 		}
 
 		// But clone the pin for each module instance

src/V3LinkCells.cpp

@@ -335,7 +335,8 @@ private:
 			    UINFO(9,"    need .* PORT  "<<portp<<endl);
 			    // Create any not already connected
 			    AstPin* newp = new AstPin(nodep->fileline(),0,portp->name(),
-						      new AstVarRef(nodep->fileline(),portp->name(),false));
+						      new AstParseRef(nodep->fileline(),
+								      AstParseRefExp::PX_TEXT, portp->name(), NULL, NULL));
 			    newp->svImplicit(true);
 			    nodep->addPinsp(newp);
 			} else {  // warn on the CELL that needs it, not the port

src/V3LinkDot.cpp

@@ -445,6 +445,10 @@ public:
 		      <<") <- se"<<srcp<<" "<<srcp->nodep()<<endl);
 		// srcp should be an interface reference pointing to the interface we want to import
 		lhsp->importFromIface(symsp(), srcp);
+		// Allow access to objects not permissible to be listed in a modport
+		if (srcp->nodep()->castModport()) {
+		    lhsp->importFromIface(symsp(), srcp->parentp(), true);
+		}
 	    }
 	    //m_scopeAliasMap[samn].clear();  // Done with it, but put into debug file
 	}
@@ -839,7 +843,7 @@ class LinkDotFindVisitor : public AstNVisitor {
     virtual void visit(AstNodeFTask* nodep) {
 	// NodeTask: Remember its name for later resolution
 	UINFO(5,"   "<<nodep<<endl);
-	if (!m_curSymp || !m_modSymp) nodep->v3fatalSrc("Function/Task not under module??\n");
+	if (!m_curSymp || !m_modSymp) nodep->v3fatalSrc("Function/Task not under module?");
 	// Remember the existing symbol table scope
 	VSymEnt* oldCurSymp = m_curSymp;
 	{
@@ -873,7 +877,7 @@ class LinkDotFindVisitor : public AstNVisitor {
     }
     virtual void visit(AstVar* nodep) {
 	// Var: Remember its name for later resolution
-	if (!m_curSymp || !m_modSymp) nodep->v3fatalSrc("Var not under module??\n");
+	if (!m_curSymp || !m_modSymp) nodep->v3fatalSrc("Var not under module?");
 	nodep->iterateChildren(*this);
 	if (!m_statep->forScopeCreation()) {
 	    // Find under either a task or the module's vars
@@ -957,12 +961,12 @@ class LinkDotFindVisitor : public AstNVisitor {
     }
     virtual void visit(AstTypedef* nodep) {
 	// Remember its name for later resolution
-	if (!m_curSymp) nodep->v3fatalSrc("Typedef not under module??\n");
+	if (!m_curSymp) nodep->v3fatalSrc("Typedef not under module?");
 	nodep->iterateChildren(*this);
 	m_statep->insertSym(m_curSymp, nodep->name(), nodep, m_packagep);
     }
     virtual void visit(AstParamTypeDType* nodep) {
-	if (!m_curSymp) nodep->v3fatalSrc("Parameter type not under module??\n");
+	if (!m_curSymp) nodep->v3fatalSrc("Parameter type not under module?");
 	nodep->iterateChildren(*this);
 	m_statep->insertSym(m_curSymp, nodep->name(), nodep, m_packagep);
     }
@@ -1593,7 +1597,7 @@ private:
 	checkNoDot(nodep);
 	nodep->iterateChildren(*this);
 	if (!nodep->modVarp()) {
-	    if (!m_pinSymp) nodep->v3fatalSrc("Pin not under cell?\n");
+	    if (!m_pinSymp) nodep->v3fatalSrc("Pin not under cell?");
 	    VSymEnt* foundp = m_pinSymp->findIdFlat(nodep->name());
 	    const char* whatp = nodep->param() ? "parameter pin" : "pin";
 	    if (!foundp) {
@@ -1861,7 +1865,7 @@ private:
 	    }
 	    //
 	    if (!ok) {
-                //Cells/interfaces can't be implicit
+                // Cells/interfaces can't be implicit
 		bool isCell = foundp ? foundp->nodep()->castCell() != NULL : false;
 		bool checkImplicit = (!m_ds.m_dotp && m_ds.m_dotText=="" && !isCell);
 		bool err = !(checkImplicit && m_statep->implicitOk(m_modp, nodep->name()));

src/V3LinkLValue.cpp

@@ -174,8 +174,10 @@ private:
     virtual void visit(AstValuePlusArgs* nodep) {
 	bool last_setRefLvalue = m_setRefLvalue;
 	{
+	    m_setRefLvalue = false;
+	    nodep->searchp()->iterateAndNext(*this);
 	    m_setRefLvalue = true;
-	    nodep->exprsp()->iterateAndNext(*this);
+	    nodep->outp()->iterateAndNext(*this);
 	}
 	m_setRefLvalue = last_setRefLvalue;
     }

src/V3LinkResolve.cpp

@@ -236,12 +236,12 @@ private:
 
     virtual void visit(AstPragma* nodep) {
 	if (nodep->pragType() == AstPragmaType::PUBLIC_MODULE) {
-	    if (!m_modp) nodep->v3fatalSrc("PUBLIC_MODULE not under a module\n");
+	    if (!m_modp) nodep->v3fatalSrc("PUBLIC_MODULE not under a module");
 	    m_modp->modPublic(true);
 	    nodep->unlinkFrBack(); pushDeletep(nodep); VL_DANGLING(nodep);
 	}
 	else if (nodep->pragType() == AstPragmaType::PUBLIC_TASK) {
-	    if (!m_ftaskp) nodep->v3fatalSrc("PUBLIC_TASK not under a task\n");
+	    if (!m_ftaskp) nodep->v3fatalSrc("PUBLIC_TASK not under a task");
 	    m_ftaskp->taskPublic(true);
 	    m_modp->modPublic(true);  // Need to get to the task...
 	    nodep->unlinkFrBack(); pushDeletep(nodep); VL_DANGLING(nodep);

src/V3Number.cpp

@@ -48,7 +48,7 @@ V3Number::V3Number(VerilogStringLiteral, FileLine* fileline, const string& str)
 	    }
 	}
     }
-    opCleanThis();
+    opCleanThis(true);
 }
 
 V3Number::V3Number (FileLine* fileline, const char* sourcep) {
@@ -254,7 +254,7 @@ V3Number::V3Number (FileLine* fileline, const char* sourcep) {
 	setBit(obit, bitIs(obit-1));
 	obit++;
     }
-    opCleanThis();
+    opCleanThis(true);
 
     //printf("Dump \"%s\"  CP \"%s\"  B '%c' %d W %d\n", sourcep, value_startp, base, width(), m_value[0]);
 }
@@ -1217,6 +1217,9 @@ V3Number& V3Number::opShiftR (const V3Number& lhs, const V3Number& rhs) {
     // L(lhs) bit return
     if (rhs.isFourState()) return setAllBitsX();
     setZero();
+    for (int bit=32; bit<rhs.width(); bit++) {
+	if (rhs.bitIs1(bit)) return *this;  // shift of over 2^32 must be zero
+    }
     uint32_t rhsval = rhs.toUInt();
     if (rhsval < (uint32_t)lhs.width()) {
 	for (int bit=0; bit<this->width(); bit++) {
@@ -1232,6 +1235,13 @@ V3Number& V3Number::opShiftRS (const V3Number& lhs, const V3Number& rhs, uint32_
     // We presume it is signed; as that's V3Width's job to convert to opShiftR
     if (rhs.isFourState()) return setAllBitsX();
     setZero();
+    for (int bit=32; bit<rhs.width(); bit++) {
+	for (int bit=0; bit<this->width(); bit++) {
+	    setBit(bit,lhs.bitIs(lbits-1)); // 0/1/X/Z
+	}
+	if (rhs.bitIs1(lbits-1)) setAllBits1(); // -1 else 0
+	return *this;  // shift of over 2^32 must be -1/0
+    }
     uint32_t rhsval = rhs.toUInt();
     if (rhsval < (uint32_t)lhs.width()) {
 	for (int bit=0; bit<this->width(); bit++) {
@@ -1239,7 +1249,7 @@ V3Number& V3Number::opShiftRS (const V3Number& lhs, const V3Number& rhs, uint32_
 	}
     } else {
 	for (int bit=0; bit<this->width(); bit++) {
-	    setBit(bit,lhs.bitIs(lbits-1));
+	    setBit(bit,lhs.bitIs(lbits-1)); // 0/1/X/Z
 	}
     }
     return *this;
@@ -1249,6 +1259,9 @@ V3Number& V3Number::opShiftL (const V3Number& lhs, const V3Number& rhs) {
     // L(lhs) bit return
     if (rhs.isFourState()) return setAllBitsX();
     setZero();
+    for (int bit=32; bit<rhs.width(); bit++) {
+	if (rhs.bitIs1(bit)) return *this;  // shift of over 2^32 must be zero
+    }
     uint32_t rhsval = rhs.toUInt();
     for (int bit=0; bit<this->width(); bit++) {
 	if (bit >= (int)rhsval) {
@@ -1518,8 +1531,6 @@ V3Number& V3Number::opPow (const V3Number& lhs, const V3Number& rhs, bool lsign,
     if (lhs.isFourState() || rhs.isFourState()) return setAllBitsX();
     if (rhs.isEqZero()) return setQuad(1); // Overrides lhs 0 -> return 0
     // We may want to special case when the lhs is 2, so we can get larger outputs
-    if (lhs.width()>64) m_fileline->v3fatalSrc("Unsupported: Large >64bit ** power operator not implemented yet: "<<*this);
-    if (rhs.width()>64) m_fileline->v3fatalSrc("Unsupported: Large >64bit ** power operator not implemented yet: "<<*this);
     if (rsign && rhs.isNegative()) {
 	if (lhs.isEqZero()) return setAllBitsXRemoved();
 	else if (lhs.isEqOne()) return setQuad(1);
@@ -1587,10 +1598,16 @@ V3Number& V3Number::opClean (const V3Number& lhs, uint32_t bits) {
     return opSel(lhs, bits-1, 0);
 }
 
-void V3Number::opCleanThis() {
-    // Clean in place number
-    m_value[words()-1]  &= hiWordMask();
-    m_valueX[words()-1] &= hiWordMask();
+void V3Number::opCleanThis(bool warnOnTruncation) {
+    // Clean MSB of number
+    uint32_t newValueMsb = m_value[words()-1]  & hiWordMask();
+    uint32_t newValueXMsb = m_valueX[words()-1] & hiWordMask();
+    if (warnOnTruncation && (newValueMsb != m_value[words()-1] || newValueXMsb != m_valueX[words()-1])) {
+	// Displaying in decimal avoids hiWordMask truncation
+	m_fileline->v3warn(WIDTH,"Value too large for "<<width()<<" bit number: "<<displayed(m_fileline, "%d"));
+    }
+    m_value[words()-1]  = newValueMsb;
+    m_valueX[words()-1] = newValueXMsb;
 }
 
 V3Number& V3Number::opSel (const V3Number& lhs, const V3Number& msb, const V3Number& lsb) {

src/V3Number.h

@@ -45,7 +45,7 @@ class V3Number {
     // METHODS
     V3Number& setSingleBits(char value);
     V3Number& setString(const string& str) { m_isString=true; m_stringVal=str; return *this; }
-    void opCleanThis();
+    void opCleanThis(bool warnOnTruncation = false);
 public:
     FileLine*	fileline() const { return m_fileline; }
     void	fileline(FileLine* fl) { m_fileline=fl; }

src/V3Number_test.cpp

@@ -84,7 +84,7 @@ void test(string lhss, string op, string rhss, string exps) {
     V3Number ok (new FileLine("ck",__LINE__), 1);
     ok.opCaseEq(expnum,gotnum);
     if (ok.toUInt()!=1) {
-	v3fatalSrc("%Error:Test FAILED\n");
+	v3fatalSrc("%Error:Test FAILED");
     }
 }
 

src/V3Options.cpp

@@ -560,7 +560,7 @@ string V3Options::version() {
 
 void V3Options::throwSigsegv() {
     // cppcheck-suppress nullPointer
-    char* zp=NULL; *zp=0;
+    char* zp=NULL; *zp=0; // Intentional core dump, ignore warnings here
 }
 
 //######################################################################
@@ -607,7 +607,7 @@ bool V3Options::onoff(const char* sw, const char* arg, bool& flag) {
     // if sw=="-no-arg", then return true (found it), and flag=false
     // if sw=="-noarg", then return true (found it), and flag=false
     // else return false
-    if (arg[0]!='-') v3fatalSrc("OnOff switches must have leading dash.\n");
+    if (arg[0]!='-') v3fatalSrc("OnOff switches must have leading dash");
     if (0==strcmp(sw,arg)) { flag=true; return true; }
     else if (0==strncmp(sw,"-no",3) && (0==strcmp(sw+3,arg+1))) { flag=false; return true; }
     else if (0==strncmp(sw,"-no-",4) && (0==strcmp(sw+4,arg+1))) { flag=false; return true; }

src/V3Order.cpp

@@ -194,7 +194,7 @@ public:
     // METHODS
     OrderVarVertex* newVarUserVertex(V3Graph* graphp, AstScope* scopep,
 				     AstVarScope* varscp, WhichVertex type, bool* createdp=NULL) {
-	if (type>=WV_MAX) varscp->v3fatalSrc("Bad Case\n");
+	if (type>=WV_MAX) varscp->v3fatalSrc("Bad case");
 	OrderVarVertex* vertexp = m_vertexp[type];
 	if (!vertexp) {
 	    UINFO(6,"New vertex "<<varscp<<endl);
@@ -205,7 +205,7 @@ public:
 	    case WV_PORD: vertexp = new OrderVarPordVertex  (graphp, scopep, varscp); break;
 	    case WV_POST: vertexp = new OrderVarPostVertex  (graphp, scopep, varscp); break;
 	    case WV_SETL: vertexp = new OrderVarSettleVertex(graphp, scopep, varscp); break;
-	    default: varscp->v3fatalSrc("Bad Case\n");
+	    default: varscp->v3fatalSrc("Bad case");
 	    }
 	    m_vertexp[type] = vertexp;
 	} else {
@@ -806,15 +806,15 @@ private:
     virtual void visit(AstNodeVarRef* nodep) {
 	if (m_scopep) {
 	    AstVarScope* varscp = nodep->varScopep();
-	    if (!varscp) nodep->v3fatalSrc("Var didn't get varscoped in V3Scope.cpp\n");
+	    if (!varscp) nodep->v3fatalSrc("Var didn't get varscoped in V3Scope.cpp");
 	    if (m_inSenTree) {
 		// Add CLOCK dependency... This is a root of the tree we'll trace
-		if (nodep->lvalue()) nodep->v3fatalSrc("How can a sensitivity be setting a var?\n");
+		if (nodep->lvalue()) nodep->v3fatalSrc("How can a sensitivity be setting a var?");
 		OrderVarVertex* varVxp = newVarUserVertex(varscp, WV_STD);
 		varVxp->isClock(true);
 		new OrderEdge(&m_graph, varVxp, m_activeSenVxp, WEIGHT_MEDIUM);
 	    } else {
-		if (!m_logicVxp) nodep->v3fatalSrc("Var ref not under a logic block\n");
+		if (!m_logicVxp) nodep->v3fatalSrc("Var ref not under a logic block");
 		// What new directions is this used
 		// We don't want to add extra edges if the logic block has many usages of same var
 		bool gen = false;

src/V3Param.cpp

@@ -204,7 +204,7 @@ private:
 		pinp->modPTypep(cloneiter->second->castParamTypeDType());
 	    }
 	    else {
-		pinp->v3fatalSrc("Not linked?\n");
+		pinp->v3fatalSrc("Not linked?");
 	    }
 	}
     }
@@ -283,7 +283,59 @@ private:
     virtual void visit(AstVarRef* nodep) {
 	if (nodep->varp()) nodep->varp()->iterate(*this);
     }
+    bool ifaceParamReplace(AstVarXRef* nodep, AstNode* candp) {
+	for (; candp; candp = candp->nextp()) {
+	    if (nodep->name() == candp->name()) {
+		if (AstVar* varp = candp->castVar()) {
+		    UINFO(9,"Found interface parameter: "<<varp<<endl);
+		    nodep->varp(varp);
+		    return true;
+		} else if (AstPin* pinp = candp->castPin()) {
+		    UINFO(9,"Found interface parameter: "<<pinp<<endl);
+		    if (!pinp->exprp()) pinp->v3fatalSrc("Interface parameter pin missing expression");
+		    nodep->replaceWith(pinp->exprp()->cloneTree(false)); VL_DANGLING(nodep);
+		    return true;
+		}
+	    }
+	}
+	return false;
+    }
     virtual void visit(AstVarXRef* nodep) {
+	// Check to see if the scope is just an interface because interfaces are special
+	string dotted = nodep->dotted();
+	if (!dotted.empty() && nodep->varp() && nodep->varp()->isParam()) {
+	    AstNode* backp = nodep;
+	    while ((backp = backp->backp())) {
+		if (backp->castNodeModule()) {
+		    UINFO(9,"Hit module boundary, done looking for interface"<<endl);
+		    break;
+		}
+		if (backp->castVar()
+		    && backp->castVar()->isIfaceRef()
+		    && backp->castVar()->childDTypep()
+		    && backp->castVar()->childDTypep()->castIfaceRefDType()) {
+		    AstIfaceRefDType* ifacerefp = backp->castVar()->childDTypep()->castIfaceRefDType();
+		    // Interfaces passed in on the port map have ifaces
+		    if (AstIface* ifacep = ifacerefp->ifacep()) {
+			if (dotted == backp->name()) {
+			    UINFO(9,"Iface matching scope:  "<<ifacep<<endl);
+			    if (ifaceParamReplace(nodep, ifacep->stmtsp())) {
+				return;
+			    }
+			}
+		    }
+		    // Interfaces declared in this module have cells
+		    else if (AstCell* cellp = ifacerefp->cellp()) {
+			if (dotted == cellp->name()) {
+			    UINFO(9,"Iface matching scope:  "<<cellp<<endl);
+			    if (ifaceParamReplace(nodep, cellp->paramsp())) {
+				return;
+			    }
+			}
+		    }
+		}
+	    }
+	}
 	nodep->varp(NULL);  // Needs relink, as may remove pointed-to var
     }
 
@@ -493,6 +545,12 @@ void ParamVisitor::visitCell(AstCell* nodep) {
 	    if (AstVar* modvarp = pinp->modVarp()) {
 		if (!modvarp->isGParam()) {
 		    pinp->v3error("Attempted parameter setting of non-parameter: Param "<<pinp->prettyName()<<" of "<<nodep->prettyName());
+		} else if (pinp->exprp()->castInitArray()
+			   && modvarp->subDTypep()->castUnpackArrayDType()) {
+		    // Array assigned to array
+		    AstNode* exprp = pinp->exprp();
+		    longname += "_" + paramSmallName(nodep->modp(),modvarp)+paramValueNumber(exprp);
+		    any_overrides = true;
 		} else {
 		    AstConst* exprp = pinp->exprp()->castConst();
 		    AstConst* origp = modvarp->valuep()->castConst();
@@ -651,11 +709,11 @@ void ParamVisitor::visitCell(AstCell* nodep) {
 		for (AstPin* pinp = nodep->paramsp(); pinp; pinp=pinp->nextp()->castPin()) {
 		    if (pinp->exprp()) {
 			if (AstVar* modvarp = pinp->modVarp()) {
-			    AstConst* constp = pinp->exprp()->castConst();
+			    AstNode* newp = pinp->exprp();  // Const or InitArray
 			    // Remove any existing parameter
 			    if (modvarp->valuep()) modvarp->valuep()->unlinkFrBack()->deleteTree();
 			    // Set this parameter to value requested by cell
-			    modvarp->valuep(constp->cloneTree(false));
+			    modvarp->valuep(newp->cloneTree(false));
 			}
 			else if (AstParamTypeDType* modptp = pinp->modPTypep()) {
 			    AstNodeDType* dtypep = pinp->exprp()->castNodeDType();

src/V3Simulate.h

@@ -44,12 +44,25 @@
 #include "V3Task.h"
 
 #include <deque>
+#include <sstream>
 
 //============================================================================
 
 //######################################################################
 // Simulate class functions
 
+class SimulateStackNode {
+public:
+    // MEMBERS
+    AstFuncRef*		m_funcp;
+    V3TaskConnects*	m_tconnects;
+    // CONSTRUCTORS
+    SimulateStackNode(AstFuncRef* funcp, V3TaskConnects* tconnects):
+	m_funcp(funcp),
+	m_tconnects(tconnects) {}
+    ~SimulateStackNode() {}
+};
+
 class SimulateVisitor : public AstNVisitor {
     // Simulate a node tree, returning value of variables
     // Two major operating modes:
@@ -90,6 +103,7 @@ private:
     // Simulating:
     deque<V3Number*>	m_numFreeps;	///< List of all numbers free and not in use
     deque<V3Number*>	m_numAllps; 	///< List of all numbers free and in use
+    deque<SimulateStackNode*>	m_callStack;	///< Call stack for verbose error messages
 
     // Cleanup
     // V3Numbers that represents strings are a bit special and the API for V3Number does not allow changing them.
@@ -103,6 +117,54 @@ private:
 	return level;
     }
 
+    // Potentially very slow, intended for debugging
+    string prettyNumber(V3Number* nump, AstNodeDType* dtypep) {
+	if (AstRefDType* refdtypep = dtypep->castRefDType()) {
+	    dtypep = refdtypep->skipRefp();
+	}
+	if (AstStructDType* stp = dtypep->castStructDType()) {
+	    if (stp->packed()) {
+		ostringstream out;
+		out<<"'{";
+		for (AstMemberDType* itemp = stp->membersp(); itemp; itemp=itemp->nextp()->castMemberDType()) {
+		    int width = itemp->width();
+		    int lsb = itemp->lsb();
+		    int msb = lsb + width - 1;
+		    V3Number fieldNum = V3Number(nump->fileline(), width);
+		    fieldNum.opSel(*nump, msb, lsb);
+		    out<<itemp->name()<<": ";
+		    if (AstNodeDType * childTypep = itemp->subDTypep()) {
+			out<<prettyNumber(&fieldNum, childTypep);
+		    } else {
+			out<<fieldNum;
+		    }
+		    if (itemp->nextp()) out<<", ";
+		}
+		out<<"}";
+		return out.str();
+	    }
+	} else if (AstPackArrayDType * arrayp = dtypep->castPackArrayDType()) {
+	    if (AstNodeDType * childTypep = arrayp->subDTypep()) {
+		ostringstream out;
+		out<<"[";
+		int arrayElements = arrayp->elementsConst();
+		for (int element = 0; element < arrayElements; ++element) {
+		    int width = childTypep->width();
+		    int lsb = width * element;
+		    int msb = lsb + width - 1;
+		    V3Number fieldNum = V3Number(nump->fileline(), width);
+		    fieldNum.opSel(*nump, msb, lsb);
+		    int arrayElem = arrayp->lsb() + element;
+		    out<<arrayElem<<" = "<<prettyNumber(&fieldNum, childTypep);
+		    if (element < arrayElements - 1) out<<", ";
+		}
+		out<<"]";
+		return out.str();
+	    }
+	}
+	return nump->ascii();
+    }
+
     // Checking METHODS
 public:
     /// Call other-this function on all new *non-constant* var references
@@ -119,6 +181,19 @@ public:
 		cout<<endl;
 	    }
 	    m_whyNotOptimizable = why;
+	    ostringstream stack;
+	    for (deque<SimulateStackNode*>::iterator it=m_callStack.begin(); it !=m_callStack.end(); ++it) {
+		AstFuncRef* funcp = (*it)->m_funcp;
+		stack<<"\nCalled from:\n"<<funcp->fileline()<<" "<<funcp->prettyName()<<"() with parameters:";
+		V3TaskConnects* tconnects = (*it)->m_tconnects;
+		for (V3TaskConnects::iterator conIt = tconnects->begin(); conIt != tconnects->end(); ++conIt) {
+		    AstVar* portp = conIt->first;
+		    AstNode* pinp = conIt->second->exprp();
+		    AstNodeDType* dtypep = pinp->dtypep();
+		    stack<<"\n    "<<portp->prettyName()<<" = "<<prettyNumber(fetchNumber(pinp), dtypep);
+		}
+	    }
+	    m_whyNotOptimizable += stack.str();
 	}
     }
     inline bool optimizable() const { return m_whyNotNodep==NULL; }
@@ -718,8 +793,11 @@ private:
 		}
 	    }
 	}
+	SimulateStackNode stackNode(nodep, &tconnects);
+	m_callStack.push_front(&stackNode);
 	// Evaluate the function
 	funcp->accept(*this);
+	m_callStack.pop_front();
 	if (!m_checkOnly && optimizable()) {
 	    // Grab return value from output variable (if it's a function)
 	    if (!funcp->fvarp()) nodep->v3fatalSrc("Function reference points at non-function");

src/V3Split.cpp

@@ -272,12 +272,12 @@ private:
 	//UINFO(9,"    push "<<nodep<<endl);
 	SplitLogicVertex* vertexp = new SplitLogicVertex(&m_graph, nodep);
 	m_stmtStackps.push_back(vertexp);
-	if (nodep->user3p()) nodep->v3fatalSrc("user3p should not be used; cleared in processBlock\n");
+	if (nodep->user3p()) nodep->v3fatalSrc("user3p should not be used; cleared in processBlock");
 	nodep->user3p(vertexp);
     }
     void scoreboardPopStmt() {
 	//UINFO(9,"    pop"<<endl);
-	if (m_stmtStackps.empty()) v3fatalSrc("Stack underflow\n");
+	if (m_stmtStackps.empty()) v3fatalSrc("Stack underflow");
 	m_stmtStackps.pop_back();
     }
 
@@ -346,8 +346,8 @@ private:
 	    SplitLogicVertex* vvertexp = (SplitLogicVertex*)nextp->user3p();
 	    vvertexp->splitColor(vvertexp->color());
 	    uint32_t color = vvertexp->splitColor();
-	    if (color >= numVertexes) nextp->v3fatalSrc("More colors than vertexes!\n");
-	    if (!color) nextp->v3fatalSrc("No node color assigned\n");
+	    if (color >= numVertexes) nextp->v3fatalSrc("More colors than vertexes");
+	    if (!color) nextp->v3fatalSrc("No node color assigned");
 	    if (lastOfColor[color]) {
 		new SplitStrictEdge(&m_graph, lastOfColor[color], vvertexp);
 	    }

src/V3SymTable.h

@@ -183,16 +183,19 @@ public:
 	}
 	return any;
     }
-    void importFromIface(VSymGraph* graphp, const VSymEnt* srcp) {
+    void importFromIface(VSymGraph* graphp, const VSymEnt* srcp, bool onlyUnmodportable = false) {
 	// Import interface tokens from source symbol table into this symbol table, recursively
 	UINFO(9, "     importIf  se"<<(void*)this<<" from se"<<(void*)srcp<<endl);
 	for (IdNameMap::const_iterator it=srcp->m_idNameMap.begin(); it!=srcp->m_idNameMap.end(); ++it) {
 	    const string& name = it->first;
 	    VSymEnt* subSrcp = it->second;
-	    VSymEnt* subSymp = new VSymEnt(graphp, subSrcp);
-	    reinsert(name, subSymp);
-	    // And recurse to create children
-	    subSymp->importFromIface(graphp, subSrcp);
+	    AstVar* varp = subSrcp->nodep()->castVar();
+	    if (!onlyUnmodportable || (varp && varp->varType() == AstVarType::GPARAM)) {
+		VSymEnt* subSymp = new VSymEnt(graphp, subSrcp);
+		reinsert(name, subSymp);
+		// And recurse to create children
+		subSymp->importFromIface(graphp, subSrcp);
+	    }
 	}
     }
     void cellErrorScopes(AstNode* lookp, string prettyName="") {

src/V3Task.cpp

@@ -263,7 +263,7 @@ private:
 	if (nodep->varp()->user2p()) { // It's being converted to a alias.
 	    UINFO(9, "    relinkVar "<<(void*)nodep->varp()->user2p()<<" "<<nodep<<endl);
 	    AstVarScope* newvscp = nodep->varp()->user2p()->castVarScope();
-	    if (!newvscp) nodep->v3fatalSrc("Null?\n");
+	    if (!newvscp) nodep->v3fatalSrc("not linked");
 	    nodep->varScopep(newvscp);
 	    nodep->varp(nodep->varScopep()->varp());
 	    nodep->name(nodep->varp()->name());
@@ -1147,7 +1147,7 @@ private:
 	m_insStmtp = NULL;	// Next thing should be new statement
     }
     virtual void visit(AstNodeFor* nodep) {
-	nodep->v3fatalSrc("For statements should have been converted to while statements in V3Begin.cpp\n");
+	nodep->v3fatalSrc("For statements should have been converted to while statements in V3Begin.cpp");
     }
     virtual void visit(AstNodeStmt* nodep) {
 	m_insMode = IM_BEFORE;

src/V3Unknown.cpp

@@ -387,7 +387,7 @@ private:
 	    } else if (basefromp->castConst()) {
 		// If it's a PARAMETER[bit], then basefromp may be a constant instead of a varrefp
 	    } else {
-		nodep->v3fatalSrc("No VarRef or Const under ArraySel\n");
+		nodep->v3fatalSrc("No VarRef or Const under ArraySel");
 	    }
 	    // Find range of dtype we are selecting from
 	    int declElements = -1;

src/V3Width.cpp

@@ -803,7 +803,6 @@ private:
 	    nodep->dtypeFrom(expDTypep);
 	    // rhs already finalized in iterate_shift_prelim
 	    iterateCheck(nodep,"LHS",nodep->lhsp(),SELF,FINAL,nodep->dtypep(),EXTEND_EXP);
-	    if (nodep->width()>64) nodep->v3error("Unsupported: Large >64bit ** power operator not implemented.");
 	    AstNode* newp = NULL;  // No change
 	    if (nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned()) {
 		newp = new AstPowSS (nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
@@ -2094,8 +2093,9 @@ private:
     }
     virtual void visit(AstValuePlusArgs* nodep) {
 	if (m_vup->prelim()) {
-	    userIterateAndNext(nodep->exprsp(), WidthVP(SELF,BOTH).p());
-	    nodep->dtypeSetSigned32();  // Spec says integer return
+	    userIterateAndNext(nodep->searchp(), WidthVP(SELF,BOTH).p());
+	    userIterateAndNext(nodep->outp(), WidthVP(SELF,BOTH).p());
+	    nodep->dtypeChgWidthSigned(32,1,AstNumeric::SIGNED);  // Spec says integer return
 	}
     }
     virtual void visit(AstUCStmt* nodep) {
@@ -2136,7 +2136,8 @@ private:
 	    AstNodeDType* subDTypep = pinDTypep;
 	    int pinwidth = pinDTypep->width();
 	    int conwidth = conDTypep->width();
-	    if (conDTypep == pinDTypep) {  // If match, we're golden
+	    if (conDTypep == pinDTypep  // If match, we're golden
+		|| similarDTypeRecurse(conDTypep, pinDTypep)) {
 		userIterateAndNext(nodep->exprp(), WidthVP(subDTypep,FINAL).p());
 	    }
 	    else if (m_cellRangep) {
@@ -2178,22 +2179,22 @@ private:
                 }
 
 		// TODO Simple dtype checking, should be a more general check
-		AstNodeArrayDType* loArrayp = exprDTypep->skipRefp()->castUnpackArrayDType();
-		AstNodeArrayDType* hiArrayp = modDTypep->skipRefp()->castUnpackArrayDType();
-		if (loArrayp && hiArrayp && loArrayp->subDTypep()->skipRefp()->castIfaceRefDType() 
-		    && loArrayp->declRange().elements() != hiArrayp->declRange().elements()) {
-		    int loSize = loArrayp->declRange().elements();
-		    int hiSize = hiArrayp->declRange().elements();
+		AstNodeArrayDType* exprArrayp = exprDTypep->skipRefp()->castUnpackArrayDType();
+		AstNodeArrayDType* modArrayp = modDTypep->skipRefp()->castUnpackArrayDType();
+		if (exprArrayp && modArrayp && exprArrayp->subDTypep()->skipRefp()->castIfaceRefDType() 
+		    && exprArrayp->declRange().elements() != modArrayp->declRange().elements()) {
+		    int exprSize = exprArrayp->declRange().elements();
+		    int modSize = modArrayp->declRange().elements();
 		    nodep->v3error("Illegal "<<nodep->prettyOperatorName()<<","
-				   <<" mismatch between port which is an interface array of size "<<loSize<<","
-				   <<" and expression which is an interface array of size "<<hiSize<<".");
+				   <<" mismatch between port which is an interface array of size "<<modSize<<","
+				   <<" and expression which is an interface array of size "<<exprSize<<".");
 		    UINFO(1,"    Related lo: "<<modDTypep->skipRefp()<<endl);
 		    UINFO(1,"    Related hi: "<<exprDTypep->skipRefp()<<endl);
-		} else if ((loArrayp && !hiArrayp && pinwidth != conwidth)
-			   || (!loArrayp && hiArrayp && pinwidth != conwidth)) {
+		} else if ((exprArrayp && !modArrayp && pinwidth != conwidth)
+			   || (!exprArrayp && modArrayp && pinwidth != conwidth)) {
 		    nodep->v3error("Illegal "<<nodep->prettyOperatorName()<<","
-				   <<" mismatch between port which is"<<(loArrayp?"":" not")<<" an array,"
-				   <<" and expression which is"<<(hiArrayp?"":" not")<<" an array.");
+				   <<" mismatch between port which is"<<(modArrayp?"":" not")<<" an array,"
+				   <<" and expression which is"<<(exprArrayp?"":" not")<<" an array.");
 		    UINFO(1,"    Related lo: "<<modDTypep->skipRefp()<<endl);
 		    UINFO(1,"    Related hi: "<<exprDTypep->skipRefp()<<endl);
 		}
@@ -2748,6 +2749,8 @@ private:
 	    AstNodeDType* expDTypep = m_vup->dtypeOverridep(nodep->dtypep());
 	    AstNodeDType* subDTypep = expDTypep;
 	    nodep->dtypeFrom(expDTypep);
+	    // We don't use LHS && RHS -- unspecified language corner, see t_math_signed5 test
+	    //bool expSigned = (nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned());
 	    if (AstNodeBiop* newp=replaceWithUOrSVersion(nodep, expDTypep->isSigned())) { VL_DANGLING(nodep);
 		nodep = newp;  // Process new node instead
 	    }
@@ -2909,6 +2912,9 @@ private:
 	return false; // No change
     }
 
+    bool similarDTypeRecurse(AstNodeDType* node1p, AstNodeDType* node2p) {
+	return node1p->skipRefp()->similarDType(node2p->skipRefp());
+    }
     void iterateCheckFileDesc (AstNode* nodep, AstNode* underp, Stage stage) {
 	if (stage != BOTH) nodep->v3fatalSrc("Bad call");
 	// underp may change as a result of replacement

src/V3WidthSel.cpp

@@ -223,7 +223,11 @@ private:
 	    // SELBIT(array, index) -> SEL(array, index*width-of-subindex, width-of-subindex)
 	    AstNode* subp = rhsp;
 	    if (fromRange.lo()!=0 || fromRange.hi()<0) {
-		subp = newSubNeg (subp, fromRange.lo());
+		if (fromRange.littleEndian()) {
+		    subp = newSubNeg(fromRange.hi(), subp);
+		} else {
+		    subp = newSubNeg(subp, fromRange.lo());
+		}
 	    }
 	    if (!fromRange.elements() || (adtypep->width() % fromRange.elements())!=0)
 		adtypep->v3fatalSrc("Array extraction with width miscomputed "
@@ -311,11 +315,20 @@ private:
 	    if (!fromRange.elements() || (adtypep->width() % fromRange.elements())!=0)
 		adtypep->v3fatalSrc("Array extraction with width miscomputed "
 				    <<adtypep->width()<<"/"<<fromRange.elements());
+	    if (fromRange.littleEndian()) {
+		// Below code assumes big bit endian; just works out if we swap
+		int x = msb; msb = lsb; lsb = x;
+	    }
+	    if (lsb > msb) {
+		nodep->v3error("["<<msb<<":"<<lsb<<"] Range extract has backward bit ordering, perhaps you wanted ["<<lsb<<":"<<msb<<"]");
+		int x = msb; msb = lsb; lsb = x;
+	    }
 	    int elwidth = adtypep->width() / fromRange.elements();
 	    AstSel* newp = new AstSel (nodep->fileline(),
 				       fromp,
-				       new AstConst(nodep->fileline(),AstConst::Unsized32(),lsb*elwidth),
-				       new AstConst(nodep->fileline(),AstConst::Unsized32(),(msb-lsb+1)*elwidth));
+				       new AstMul(nodep->fileline(), newSubLsbOf(lsbp, fromRange),
+						  new AstConst(nodep->fileline(), AstConst::Unsized32(), elwidth)),
+				       new AstConst(nodep->fileline(), AstConst::Unsized32(), (msb-lsb+1)*elwidth));
 	    newp->declRange(fromRange);
 	    newp->declElWidth(elwidth);
 	    newp->dtypeFrom(sliceDType(adtypep, msb, lsb));

src/VlcMain.cpp

@@ -52,7 +52,7 @@ bool VlcOptions::onoff(const char* sw, const char* arg, bool& flag) {
     // if sw=="-no-arg", then return true (found it), and flag=false
     // if sw=="-noarg", then return true (found it), and flag=false
     // else return false
-    if (arg[0]!='-') v3fatalSrc("OnOff switches must have leading dash.\n");
+    if (arg[0]!='-') v3fatalSrc("OnOff switches must have leading dash.");
     if (0==strcmp(sw,arg)) { flag=true; return true; }
     else if (0==strncmp(sw,"-no",3) && (0==strcmp(sw+3,arg+1))) { flag=false; return true; }
     else if (0==strncmp(sw,"-no-",4) && (0==strcmp(sw+4,arg+1))) { flag=false; return true; }

src/verilog.l

@@ -873,7 +873,7 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   /* Attributes */
   /* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */
 <V95,V01,V05,VA5,S05,S09,S12,SAX>{
-    "(*"({ws}|{crnl})*({id}|{escid})	{ yymore(); yy_push_state(ATTRMODE); }	// Doesn't match (*), but (* attr_spec
+    "(*"({ws}|{crnl})*({id}|{escid})	{ yymore(); yy_push_state(ATTRMODE); }	/* Doesn't match (*), but (* attr_spec */
 }
 
   /************************************************************************/

src/verilog.y

@@ -2710,12 +2710,12 @@ system_f_call<nodep>:		// IEEE: system_tf_call (as func)
 	|	yD_SQRT '(' expr ')'			{ $$ = new AstSqrtD($1,$3); }
 	|	yD_SSCANF '(' expr ',' str commaVRDListE ')'	{ $$ = new AstSScanF($1,*$5,$3,$6); }
 	|	yD_STIME parenE				{ $$ = new AstSel($1,new AstTime($1),0,32); }
-	|	yD_SYSTEM  '(' expr ')'				{ $$ = new AstSystemF($1,$3); }
+	|	yD_SYSTEM  '(' expr ')'			{ $$ = new AstSystemF($1,$3); }
 	|	yD_TESTPLUSARGS '(' str ')'		{ $$ = new AstTestPlusArgs($1,*$3); }
 	|	yD_TIME	parenE				{ $$ = new AstTime($1); }
 	|	yD_UNPACKED_DIMENSIONS '(' expr ')'	{ $$ = new AstAttrOf($1,AstAttrType::DIM_UNPK_DIMENSIONS,$3); }
 	|	yD_UNSIGNED '(' expr ')'		{ $$ = new AstUnsigned($1,$3); }
-	|	yD_VALUEPLUSARGS '(' str ',' expr ')'	{ $$ = new AstValuePlusArgs($1,*$3,$5); }
+	|	yD_VALUEPLUSARGS '(' expr ',' expr ')'	{ $$ = new AstValuePlusArgs($1,$3,$5); }
 	;
 
 exprOrDataType<nodep>:		// expr | data_type: combined to prevent conflicts

test_regress/driver.pl

@@ -1463,9 +1463,12 @@ sub vcd_identical {
     if (!-r $fn2) { $self->error("File does not exist $fn2\n"); return 0; }
     {
 	# vcddiff to check transitions, if installed
-	my $out = `vcddiff --help`;
+	my $cmd = qq{vcddiff --help};
+	print "\t$cmd\n" if $::Debug;
+	my $out = `$cmd`;
 	if ($out !~ /Usage:/) { $self->skip("No vcddiff installed\n"); return 0; }
-	my $cmd = qq{vcddiff "$fn1" "$fn2"};
+
+	$cmd = qq{vcddiff "$fn1" "$fn2"};
 	print "\t$cmd\n" if $::Debug;
 	$out = `$cmd`;
 	if ($out ne '') {

test_regress/t/t_assert_question.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    verilator_flags2 => ['--assert'],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_assert_question.v

@@ -0,0 +1,33 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2016 by Wilson Snyder
+
+module t (/*AUTOARG*/
+   // Outputs
+   dout,
+   // Inputs
+   clk, sel, a, c
+   );
+
+   input clk;
+   input bit [3:0] sel;
+   input bit [3:0] a;
+   input bit 	   c;
+   output bit      dout;
+
+   localparam logic DC  = 1'b?;
+
+   always_ff @(posedge clk) begin
+      unique casez(sel)
+        4'b0000: dout                  <= a[0];
+        4'b001?: dout                  <= a[1];
+        {1'b0, 1'b1, 1'b?, 1'b?}: dout <= a[2];
+        {1'b1, 1'b?, 1'b?, DC}: dout   <= a[3];
+        default: dout                  <= '0;
+      endcase
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule

test_regress/t/t_clk_concat.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_clk_concat.v

@@ -0,0 +1,97 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty.
+//
+
+module some_module (
+		    input wrclk
+		    );
+
+   logic [ 1 : 0 ] 	  some_state;
+   logic [1:0] 		  some_other_state;
+
+   always @(posedge wrclk) begin
+      case (some_state)
+        2'b11:
+          if (some_other_state == 0)
+            some_state <= 2'b00;
+        default:
+          $display ("This is a display statement");
+      endcase
+
+      if (wrclk)
+        some_other_state <= 0;
+   end
+
+endmodule
+
+`define BROKEN
+
+module t1(
+	  input [3:0] i_clks,
+	  input       i_clk0,
+	  input       i_clk1
+	  );
+
+   some_module
+     some_module
+       (
+`ifdef BROKEN
+	.wrclk (i_clks[3])
+`else
+	.wrclk (i_clk1)
+`endif
+	);
+endmodule
+
+module t2(
+	  input [2:0] i_clks,
+	  input       i_clk0,
+	  input       i_clk1,
+	  input       i_clk2,
+	  input       i_data
+	  );
+   logic [3:0] 	      the_clks;
+   logic 	      data_q;
+
+   assign the_clks = {i_clk1, i_clk2, i_clk1, i_clk0};
+
+   always @(posedge i_clk0) begin
+      data_q <= i_data;
+   end
+
+   t1 t1
+     (
+      .i_clks (the_clks),
+      .i_clk0 (i_clk0),
+      .i_clk1 (i_clk1)
+      );
+endmodule
+
+module t(
+	 input clk0 /*verilator clocker*/,
+	 input clk1 /*verilator clocker*/,
+	 input clk2 /*verilator clocker*/,
+	 input data_in
+	 );
+
+   logic [2:0] clks;
+
+   assign clks = {1'b0, clk1, clk0};
+
+   t2
+     t2
+       (
+	.i_clks (clks),
+	.i_clk0 (clk0),
+	.i_clk1 (clk1),
+	.i_clk2 (clk2),
+	.i_data (data_in)
+	);
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

test_regress/t/t_clk_concat2.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_clk_concat2.v

@@ -0,0 +1,106 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty.
+//
+
+module some_module (
+		    input wrclk
+		    );
+
+   logic [ 1 : 0 ] 	  some_state;
+   logic [1:0] 		  some_other_state;
+
+   always @(posedge wrclk) begin
+      case (some_state)
+        2'b11:
+          if (some_other_state == 0)
+            some_state <= 2'b00;
+        default:
+          $display ("This is a display statement");
+      endcase
+
+      if (wrclk)
+        some_other_state <= 0;
+   end
+
+endmodule
+
+`define BROKEN
+
+module t1(
+	  input [3:0] i_clks,
+	  input       i_clk0,
+	  input       i_clk1
+	  );
+
+   some_module
+     some_module
+       (
+`ifdef BROKEN
+	.wrclk (i_clks[3])
+`else
+	.wrclk (i_clk1)
+`endif
+	);
+endmodule
+
+module t2(
+	  input [2:0] i_clks,
+	  input       i_clk0,
+	  input       i_clk1,
+	  input       i_clk2,
+	  input       i_data
+	  );
+   logic [3:0] 	      the_clks;
+   logic 	      data_q;
+
+   assign the_clks[3] = i_clk1;
+   assign the_clks[2] = i_clk2;
+   assign the_clks[1] = i_clk1;
+   assign the_clks[0] = i_clk0;
+
+   always @(posedge i_clk0) begin
+      data_q <= i_data;
+   end
+
+   t1 t1
+     (
+      .i_clks (the_clks),
+      .i_clk0 (i_clk0),
+      .i_clk1 (i_clk1)
+      );
+endmodule
+
+module t(
+	 /*AUTOARG*/
+	 // Inputs
+	 clk /*verilator clocker*/,
+	 input clk0 /*verilator clocker*/,
+	 input clk1 /*verilator clocker*/,
+	 input clk2 /*verilator clocker*/,
+	 input data_in
+	 );
+
+   input       clk;
+
+   logic [2:0] clks;
+
+   assign clks = {1'b0, clk1, clk0};
+
+   t2
+     t2
+       (
+	.i_clks (clks),
+	.i_clk0 (clk0),
+	.i_clk1 (clk),
+	.i_clk2 (clk2),
+	.i_data (data_in)
+	);
+
+   always @(posedge clk) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule

test_regress/t/t_clk_concat3.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_clk_concat3.v

@@ -0,0 +1,101 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty.
+//
+
+/* verilator lint_off LITENDIAN */
+module some_module (
+		    input wrclk
+		    );
+
+   logic [ 1 : 0 ] 	  some_state;
+   logic [1:0] 		  some_other_state;
+
+   always @(posedge wrclk) begin
+      case (some_state)
+        2'b11:
+          if (some_other_state == 0)
+            some_state <= 2'b00;
+        default:
+          $display ("This is a display statement");
+      endcase
+
+      if (wrclk)
+        some_other_state <= 0;
+   end
+
+endmodule
+
+`define BROKEN
+
+module t1(
+	  input [-12:-9] i_clks,
+	  input 	 i_clk0,
+	  input 	 i_clk1
+	  );
+
+   some_module
+     some_module
+       (
+`ifdef BROKEN
+	.wrclk (i_clks[-12])
+`else
+	.wrclk (i_clk1)
+`endif
+	);
+endmodule
+
+module t2(
+	  input [2:0] i_clks,
+	  input       i_clk0,
+	  input       i_clk1,
+	  input       i_clk2,
+	  input       i_data
+	  );
+   logic [-12:-9]     the_clks;
+   logic 	      data_q;
+
+   assign the_clks[-12] = i_clk1;
+   assign the_clks[-11] = i_clk2;
+   assign the_clks[-10] = i_clk1;
+   assign the_clks[-9] = i_clk0;
+
+   always @(posedge i_clk0) begin
+      data_q <= i_data;
+   end
+
+   t1 t1
+     (
+      .i_clks (the_clks),
+      .i_clk0 (i_clk0),
+      .i_clk1 (i_clk1)
+      );
+endmodule
+
+module t(
+	 input clk0 /*verilator clocker*/,
+	 input clk1 /*verilator clocker*/,
+	 input clk2 /*verilator clocker*/,
+	 input data_in
+	 );
+
+   logic [2:0] clks;
+
+   assign clks = {1'b0, clk1, clk0};
+
+   t2
+     t2
+       (
+	.i_clks (clks),
+	.i_clk0 (clk0),
+	.i_clk1 (clk1),
+	.i_clk2 (clk2),
+	.i_data (data_in)
+	);
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

test_regress/t/t_clk_concat4.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_clk_concat4.v

@@ -0,0 +1,105 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty.
+//
+
+module some_module (
+		    input wrclk
+		    );
+
+   logic [ 1 : 0 ] 	  some_state;
+   logic [1:0] 		  some_other_state;
+
+   always @(posedge wrclk) begin
+      case (some_state)
+        2'b11:
+          if (some_other_state == 0)
+            some_state <= 2'b00;
+        default:
+          $display ("This is a display statement");
+      endcase
+
+      if (wrclk)
+        some_other_state <= 0;
+   end
+
+endmodule
+
+`define BROKEN
+
+module t1(
+	  input [3:0] i_clks,
+	  input       i_clk0,
+	  input       i_clk1
+	  );
+
+   generate
+      genvar 	      i;
+      for (i = 0; i < 2; i = i + 1) begin: a_generate_block
+         some_module
+               some_module
+               (
+`ifdef BROKEN
+		.wrclk (i_clks[3])
+`else
+		.wrclk (i_clk1)
+`endif
+		);
+      end
+   endgenerate
+endmodule
+
+module t2(
+	  input [2:0] i_clks,
+	  input       i_clk0,
+	  input       i_clk1,
+	  input       i_clk2,
+	  input       i_data
+	  );
+   logic [3:0] 	      the_clks;
+   logic 	      data_q;
+
+   assign the_clks[3] = i_clk1;
+   assign the_clks[2] = i_clk2;
+   assign the_clks[1] = i_clk1;
+   assign the_clks[0] = i_clk0;
+
+   always @(posedge i_clk0) begin
+      data_q <= i_data;
+   end
+
+   t1 t1
+     (
+      .i_clks (the_clks),
+      .i_clk0 (i_clk0),
+      .i_clk1 (i_clk1)
+      );
+endmodule
+
+module t(
+	 input clk0 /*verilator clocker*/,
+	 input clk1 /*verilator clocker*/,
+	 input clk2 /*verilator clocker*/,
+	 input data_in
+	 );
+
+   logic [2:0] clks;
+
+   assign clks = {1'b0, clk1, clk0};
+
+   t2
+     t2
+       (
+	.i_clks (clks),
+	.i_clk0 (clk0),
+	.i_clk1 (clk1),
+	.i_clk2 (clk2),
+	.i_data (data_in)
+	);
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

test_regress/t/t_clk_concat5.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_clk_concat5.v

@@ -0,0 +1,104 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty.
+//
+
+module some_module (
+		    input [3:0] i_clks
+		    );
+
+   logic [ 1 : 0 ] 		some_state;
+   logic [1:0] 			some_other_state;
+
+   always @(posedge i_clks[3]) begin
+      case (some_state)
+        2'b11:
+          if (some_other_state == 0)
+            some_state <= 2'b00;
+        default:
+          $display ("This is a display statement");
+      endcase
+
+      if (i_clks[3])
+        some_other_state <= 0;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
+
+`define BROKEN
+
+module t1(
+	  input [3:0] i_clks,
+	  input       i_clk0,
+	  input       i_clk1
+	  );
+
+   some_module
+     some_module
+       (
+	.i_clks (i_clks)
+	);
+endmodule
+
+module t2(
+	  input [2:0] i_clks,
+	  input       i_clk0,
+	  input       i_clk1,
+	  input       i_clk2,
+	  input       i_data
+	  );
+   logic [3:0] 	      the_clks;
+   logic 	      data_q;
+
+   assign the_clks[3] = i_clk1;
+   assign the_clks[2] = i_clk2;
+   assign the_clks[1] = i_clk1;
+   assign the_clks[0] = i_clk0;
+
+   always @(posedge i_clk0) begin
+      data_q <= i_data;
+   end
+
+   t1 t1
+     (
+      .i_clks (the_clks),
+      .i_clk0 (i_clk0),
+      .i_clk1 (i_clk1)
+      );
+endmodule
+
+module t(
+	 /*AUTOARG*/
+	 // Inputs
+	 clk /*verilator clocker*/,
+	 input clk0 /*verilator clocker*/,
+	 input clk1 /*verilator clocker*/,
+	 input clk2 /*verilator clocker*/,
+	 input data_in
+	 );
+
+   input       clk;
+
+   logic [2:0] clks;
+
+   assign clks = {1'b0, clk1, clk0};
+
+   t2
+     t2
+       (
+	.i_clks (clks),
+	.i_clk0 (clk0),
+	.i_clk1 (clk),
+	.i_clk2 (clk2),
+	.i_data (data_in)
+	);
+
+   //   initial begin
+   //      $write("*-* All Finished *-*\n");
+   //      $finish;
+   //   end
+endmodule

test_regress/t/t_clk_concat6.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_clk_concat6.v

@@ -0,0 +1,113 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty.
+//
+
+module some_module (
+		    input [3:0] i_clks
+		    );
+
+   logic [ 1 : 0 ] 		some_state;
+   logic [1:0] 			some_other_state;
+   logic 			the_clk;
+   
+   assign the_clk = i_clks[3];
+
+   always @(posedge the_clk) begin
+      case (some_state)
+        2'b11:
+          if (some_other_state == 0)
+            some_state <= 2'b00;
+        default:
+          $display ("This is a display statement");
+      endcase
+
+      if (the_clk)
+        some_other_state <= 0;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
+
+`define BROKEN
+
+module t1(
+	  input [3:0] i_clks,
+	  input       i_clk0,
+	  input       i_clk1
+	  );
+
+   some_module
+     some_module
+       (
+	.i_clks (i_clks)
+	);
+endmodule
+
+module ident(
+	     input  i_ident,
+	     output o_ident
+	     );
+   assign o_ident = i_ident;
+endmodule
+
+module t2(
+	  input [2:0] i_clks,
+	  input       i_clk0,
+	  input       i_clk1,
+	  input       i_clk2,
+	  input       i_data
+	  );
+   logic [3:0] 	      the_clks;
+   logic 	      data_q;
+   logic 	      ident_clk1;
+
+   always @(posedge i_clk0) begin
+      data_q <= i_data;
+   end
+
+   ident
+     ident
+       (
+	.i_ident (i_clk1),
+	.o_ident (ident_clk1)
+	);
+
+   t1 t1
+     (
+      .i_clks ({ident_clk1, i_clk2, ident_clk1, i_clk0}),
+      .i_clk0 (i_clk0),
+      .i_clk1 (i_clk1)
+      );
+endmodule
+
+module t(
+	 /*AUTOARG*/
+	 // Inputs
+	 clk /*verilator clocker*/ /*verilator public_flat*/,
+	 input clk0 /*verilator clocker*/,
+	 input clk1 /*verilator clocker*/,
+	 input clk2 /*verilator clocker*/,
+	 input data_in
+	 );
+
+   input       clk;
+
+   logic [2:0] clks;
+
+   assign clks = {1'b0, clk1, clk0};
+
+   t2
+     t2
+       (
+	.i_clks (clks),
+	.i_clk0 (clk0),
+	.i_clk1 (clk),
+	.i_clk2 (clk2),
+	.i_data (data_in)
+	);
+
+endmodule

test_regress/t/t_func_const2_bad.pl

@@ -0,0 +1,31 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2017 by Todd Strader. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+#
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>1,
+	 expect=>
+q{%Warning-USERFATAL: f_add = 15
+%Warning-USERFATAL: Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
+%Error: t/t_func_const2_bad.v:10: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2'
+%Error: t/t_func_const2_bad.v:21: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
+Called from:
+t/t_func_const2_bad.v:26:  f_add() with parameters:
+    a = 32'h7
+    b = 32'h8
+Called from:
+t/t_func_const2_bad.v:10:  f_add2() with parameters:
+    a = ?32?sh7
+    b = ?32?sh8
+    c = ?32?sh9
+},
+	 );
+
+ok(1);
+1;

test_regress/t/t_func_const2_bad.v

@@ -0,0 +1,28 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Todd Strader.
+
+module t;
+
+   localparam P6 = f_add(5, 1);
+   localparam P14 = f_add2(2, 3, f_add(4, 5));
+   localparam P24 = f_add2(7, 8, 9);
+
+   initial begin
+      // Should never get here
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+   function integer f_add(input [31:0] a, input [31:0] b);
+      f_add = a+b;
+      if (f_add == 15)
+        $fatal(2, "f_add = 15");
+   endfunction
+
+   // Speced ok: function called from function
+   function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c);
+      f_add2 = f_add(a,b)+c;
+   endfunction
+endmodule

test_regress/t/t_func_const_bad.pl

@@ -11,24 +11,39 @@ compile (
 	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
-q{%Error: t/t_func_const_bad.v:\d+: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_output'
-%Error: t/t_func_const_bad.v:\d+: ... Location of non-constant VAR 'o': Language violation: Outputs not allowed in constant functions
-%Error: t/t_func_const_bad.v:\d+: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_dotted'
-%Error: t/t_func_const_bad.v:\d+: ... Location of non-constant VARXREF 'EIGHT': Language violation: Dotted hierarchical references not allowed in constant functions
-%Error: t/t_func_const_bad.v:\d+: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_nonparam'
-%Error: t/t_func_const_bad.v:\d+: ... Location of non-constant VARREF 'modvar': Language violation: reference to non-function-local variable
-%Error: t/t_func_const_bad.v:\d+: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_infinite'
-%Error: t/t_func_const_bad.v:\d+: ... Location of non-constant WHILE: Loop unrolling took too long; probably this is an infinite loop, or set --unroll-count above 1024
-%Error: t/t_func_const_bad.v:\d+: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_stop'
-%Error: t/t_func_const_bad.v:\d+: ... Location of non-constant STOP: .stop executed during function constification; maybe indicates assertion firing
+q{%Error: t/t_func_const_bad.v:11: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_output'
+%Error: t/t_func_const_bad.v:12: ... Location of non-constant VAR 'o': Language violation: Outputs not allowed in constant functions
+%Error: t/t_func_const_bad.v:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_dotted'
+%Error: t/t_func_const_bad.v:22: ... Location of non-constant VARXREF 'EIGHT': Language violation: Dotted hierarchical references not allowed in constant functions
+Called from:
+t/t_func_const_bad.v:20:  f_bad_dotted() with parameters:
+    a = ?32?sh2
+%Error: t/t_func_const_bad.v:27: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_nonparam'
+%Error: t/t_func_const_bad.v:29: ... Location of non-constant VARREF 'modvar': Language violation: reference to non-function-local variable
+Called from:
+t/t_func_const_bad.v:27:  f_bad_nonparam() with parameters:
+    a = ?32?sh3
+%Error: t/t_func_const_bad.v:35: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_infinite'
+%Error: t/t_func_const_bad.v:37: ... Location of non-constant WHILE: Loop unrolling took too long; probably this is an infinite loop, or set --unroll-count above 1024
+Called from:
+t/t_func_const_bad.v:35:  f_bad_infinite() with parameters:
+    a = ?32?sh3
+%Error: t/t_func_const_bad.v:43: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_stop'
+%Error: t/t_func_const_bad.v:45: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
+Called from:
+t/t_func_const_bad.v:43:  f_bad_stop() with parameters:
+    a = ?32?sh3
 -Info: Printing in loop:           0
 -Info: Printing in loop:           1
 -Info: Printing in loop:           2
 %Warning-USERFATAL: Fatal Error
-%Warning-USERFATAL: Use ... verilator lint_off USERFATAL ... and lint_on around source to disable this message.
-%Error: t/t_func_const_bad.v:\d+: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_fatal'
-%Error: t/t_func_const_bad.v:\d+: ... Location of non-constant STOP: .stop executed during function constification; maybe indicates assertion firing
-%Error: Exiting due to.*},
+%Warning-USERFATAL: Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
+%Error: t/t_func_const_bad.v:49: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_fatal'
+%Error: t/t_func_const_bad.v:54: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
+Called from:
+t/t_func_const_bad.v:49:  f_bad_fatal() with parameters:
+    a = ?32?sh3
+},
 	 );
 
 ok(1);

test_regress/t/t_func_const_packed_array_bad.pl

@@ -0,0 +1,30 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2017 by Todd Strader. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+#
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>1,
+	 expect=>
+q{%Warning-USERFATAL: f_add = 15
+%Warning-USERFATAL: Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
+%Error: t/t_func_const_packed_array_bad.v:11: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2'
+%Error: t/t_func_const_packed_array_bad.v:22: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
+Called from:
+t/t_func_const_packed_array_bad.v:30:  f_add() with parameters:
+    params = [0 = 32'h7, 1 = 32'h8]
+Called from:
+t/t_func_const_packed_array_bad.v:11:  f_add2() with parameters:
+    a = ?32?sh7
+    b = ?32?sh8
+    c = ?32?sh9
+},
+	 );
+
+ok(1);
+1;

test_regress/t/t_func_const_packed_array_bad.v

@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Todd Strader.
+
+module t;
+
+   localparam [ 1 : 0 ] [ 31 : 0 ] P = {32'd5, 32'd1};
+   localparam P6 = f_add(P);
+   localparam P14 = f_add2(2, 3, f_add(P));
+   localparam P24 = f_add2(7, 8, 9);
+
+   initial begin
+      // Should never get here
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+   function integer f_add(input [ 1 : 0 ] [ 31 : 0 ] params);
+      f_add = params[0]+params[1];
+      if (f_add == 15)
+        $fatal(2, "f_add = 15");
+   endfunction
+
+   // Speced ok: function called from function
+   function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c);
+      logic [ 1 : 0 ] [ 31 : 0 ] params;
+      params[0] = a;
+      params[1] = b;
+      f_add2 = f_add(params)+c;
+   endfunction
+endmodule

test_regress/t/t_func_const_packed_struct_bad.pl

@@ -0,0 +1,30 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2017 by Todd Strader. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+#
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>1,
+	 expect=>
+q{%Warning-USERFATAL: f_add = 15
+%Warning-USERFATAL: Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
+%Error: t/t_func_const_packed_struct_bad.v:13: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2'
+%Error: t/t_func_const_packed_struct_bad.v:24: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
+Called from:
+t/t_func_const_packed_struct_bad.v:32:  f_add() with parameters:
+    params = [0 = '{a: 32'h7, b: 32'h22b}, 1 = '{a: 32'h3039, b: 32'h8}]
+Called from:
+t/t_func_const_packed_struct_bad.v:13:  f_add2() with parameters:
+    a = ?32?sh7
+    b = ?32?sh8
+    c = ?32?sh9
+},
+	 );
+
+ok(1);
+1;

test_regress/t/t_func_const_packed_struct_bad.v

@@ -0,0 +1,34 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Todd Strader.
+
+module t;
+
+   typedef struct packed {
+      logic [ 31 : 0 ] a;
+      logic [ 31 : 0 ] b;
+   } params_t;
+
+   localparam P24 = f_add2(7, 8, 9);
+
+   initial begin
+      // Should never get here
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+   function integer f_add(input params_t [ 1 : 0 ] params);
+      f_add = params[0].a+params[1].b;
+      if (f_add == 15)
+        $fatal(2, "f_add = 15");
+   endfunction
+
+   // Speced ok: function called from function
+   function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c);
+      params_t [ 1 : 0 ] params;
+      params[0] = '{a:a, b:555};
+      params[1] = '{a:12345, b:b};
+      f_add2 = f_add(params)+c;
+   endfunction
+endmodule

test_regress/t/t_func_const_packed_struct_bad2.pl

@@ -0,0 +1,30 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2017 by Todd Strader. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+#
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>1,
+	 expect=>
+q{%Warning-USERFATAL: f_add = 15
+%Warning-USERFATAL: Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
+%Error: t/t_func_const_packed_struct_bad2.v:19: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2'
+%Error: t/t_func_const_packed_struct_bad2.v:30: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
+Called from:
+t/t_func_const_packed_struct_bad2.v:42:  f_add() with parameters:
+    params = [0 = '{a: 32'h7, foo: 6'hb, sub_params: '{b: 32'h37, bar: 8'h6f}}, 1 = '{a: 32'h3039, foo: 6'hc, sub_params: '{b: 32'h8, bar: 8'h70}}]
+Called from:
+t/t_func_const_packed_struct_bad2.v:19:  f_add2() with parameters:
+    a = ?32?sh7
+    b = ?32?sh8
+    c = ?32?sh9
+},
+	 );
+
+ok(1);
+1;

test_regress/t/t_func_const_packed_struct_bad2.v

@@ -0,0 +1,44 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Todd Strader.
+
+module t;
+
+   typedef struct packed {
+      logic [ 31 : 0 ] b;
+      logic [ 7 : 0 ]  bar;
+   } sub_params_t;
+
+   typedef struct      packed {
+      logic [ 31 : 0 ] a;
+      logic [ 5 : 0 ]  foo;
+      sub_params_t sub_params;
+   } params_t;
+
+   localparam P24 = f_add2(7, 8, 9);
+
+   initial begin
+      // Should never get here
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+   function integer f_add(input params_t [ 1 : 0 ] params);
+      f_add = params[0].a+params[1].sub_params.b;
+      if (f_add == 15)
+        $fatal(2, "f_add = 15");
+   endfunction
+
+   // Speced ok: function called from function
+   function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c);
+      params_t [ 1 : 0 ] params;
+      sub_params_t sp0;
+      sub_params_t sp1;
+      sp0 = '{b:55, bar:111};
+      params[0] = '{a:a, foo:11, sub_params:sp0};
+      sp1 = '{b:b, bar:112};
+      params[1] = '{a:12345, foo:12, sub_params:sp1};
+      f_add2 = f_add(params)+c;
+   endfunction
+endmodule

test_regress/t/t_func_const_struct_bad.pl

@@ -0,0 +1,30 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2017 by Todd Strader. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+#
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>1,
+	 expect=>
+q{%Warning-USERFATAL: f_add = 15
+%Warning-USERFATAL: Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
+%Error: t/t_func_const_struct_bad.v:16: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2'
+%Error: t/t_func_const_struct_bad.v:27: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
+Called from:
+t/t_func_const_struct_bad.v:37:  f_add() with parameters:
+    params = '{a: 32'h7, b: 32'h8}
+Called from:
+t/t_func_const_struct_bad.v:16:  f_add2() with parameters:
+    a = ?32?sh7
+    b = ?32?sh8
+    c = ?32?sh9
+},
+	 );
+
+ok(1);
+1;

test_regress/t/t_func_const_struct_bad.v

@@ -0,0 +1,39 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Todd Strader.
+
+module t;
+
+   typedef struct packed {
+      logic [ 31 : 0 ] a;
+      logic [ 31 : 0 ] b;
+   } params_t;
+
+   localparam params_t P = '{a:5, b:1};
+   localparam P6 = f_add(P);
+   localparam P14 = f_add2(2, 3, f_add(P));
+   localparam P24 = f_add2(7, 8, 9);
+
+   initial begin
+      // Should never get here
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+   function integer f_add(input params_t params);
+      f_add = params.a+params.b;
+      if (f_add == 15)
+        $fatal(2, "f_add = 15");
+   endfunction
+
+   // Speced ok: function called from function
+   function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c);
+      params_t params;
+      params = '{
+		 a: a,
+		 b: b
+		 };
+      f_add2 = f_add(params)+c;
+   endfunction
+endmodule

test_regress/t/t_inst_darray.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_inst_darray.v

@@ -0,0 +1,85 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by John Stevenson.
+
+typedef logic [63:0] uid_t;
+typedef logic [31:0] value_t;
+
+interface the_intf #(parameter M = 5);
+   logic 	     valid;
+   uid_t           uid;
+   value_t [M-1:0] values;
+
+   modport i(
+	     output valid,
+	     output uid,
+	     output values
+	     );
+   modport t(
+	     input valid,
+	     input uid,
+	     input values
+	     );
+endinterface
+
+module Contemplator #(
+		      parameter IMPL = 0,
+		      parameter M    = 5,
+		      parameter N    = 1 )
+   (
+    input logic clk,
+    the_intf.i out [N-1:0]
+    );
+
+   the_intf #(.M(M)) inp[N-1:0] ();
+
+   DeepThought #(
+		 .N    ( N   ))
+   ultimateAnswerer(
+		    .src  ( inp ),
+		    .dst  ( out ));
+endmodule
+
+module DeepThought #(
+		     parameter N = 1 )
+   (
+    the_intf.t src[N-1:0],
+    the_intf.i dst[N-1:0]
+    );
+endmodule
+
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   localparam  M = 5;
+   localparam  N = 1;
+
+   the_intf #(.M(M)) out0 [N-1:0] ();
+   the_intf #(.M(M)) out1 [N-1:0] ();
+
+   Contemplator #(
+		  .IMPL ( 0    ),
+		  .M    ( M    ),
+		  .N    ( N    ))
+   contemplatorOfTheZerothKind(
+			       .clk  ( clk  ),
+			       .out  ( out0 ));
+
+   Contemplator #(
+		  .IMPL ( 1    ),
+		  .M    ( M    ),
+		  .N    ( N    ))
+   contemplatorOfTheFirstKind(
+			      .clk  ( clk  ),
+			      .out  ( out1 ));
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule

test_regress/t/t_interface_parameter_access.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_interface_parameter_access.v

@@ -0,0 +1,89 @@
+// DESCRIPTION: Verilator: Interface parameter getter
+//
+// A test of the import parameter used with modport
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2015 by Todd Strader
+
+interface test_if #(parameter integer FOO = 1);
+
+   // Interface variable
+   logic 	data;
+
+   // Modport
+   modport mp(
+              import  getFoo,
+	      output  data
+	      );
+
+   function integer getFoo ();
+      return FOO;
+   endfunction
+
+endinterface // test_if
+
+function integer identity (input integer x);
+   return x;
+endfunction
+
+
+module t (/*AUTOARG*/
+	  // Inputs
+	  clk
+	  );
+   input clk;
+
+   test_if #( .FOO (identity(5)) ) the_interface ();
+
+   testmod testmod_i (.clk (clk),
+		      .intf (the_interface),
+                      .intf_no_mp (the_interface)
+                      );
+
+   localparam THE_TOP_FOO = the_interface.FOO;
+
+   initial begin
+      if (THE_TOP_FOO != 5) begin
+         $display("%%Error: THE_TOP_FOO = %0d", THE_TOP_FOO);
+	 $stop;
+      end
+   end
+
+endmodule
+
+
+module testmod
+  (
+   input clk,
+   test_if.mp intf,
+   test_if intf_no_mp
+   );
+
+   localparam THE_FOO = intf.FOO;
+   localparam THE_OTHER_FOO = intf_no_mp.FOO;
+
+   always @(posedge clk) begin
+      if (THE_FOO != 5) begin
+         $display("%%Error: THE_FOO = %0d", THE_FOO);
+	 $stop;
+      end
+      if (THE_OTHER_FOO != 5) begin
+         $display("%%Error: THE_OTHER_FOO = %0d", THE_OTHER_FOO);
+         $stop;
+      end
+      if (intf.FOO != 5) begin
+         $display("%%Error: intf.FOO = %0d", intf.FOO);
+	 $stop;
+      end
+      if (intf_no_mp.FOO != 5) begin
+         $display("%%Error: intf_no_mp.FOO = %0d", intf_no_mp.FOO);
+         $stop;
+      end
+      //      if (i.getFoo() != 5) begin
+      //         $display("%%Error: i.getFoo() = %0d", i.getFoo());
+      //	 $stop;
+      //      end
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

test_regress/t/t_interface_size_bad.pl

@@ -10,8 +10,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 compile (
 	fails=>1,
 	expect=>
-q{%Error: t/t_interface_size_bad.v:\d+: Illegal IFACEREF port connection 'foo', mismatch between port which is an interface array of size 4, and expression which is an interface array of size 5.
-%Error: t/t_interface_size_bad.v:\d+: Illegal IFACEREF port connection 'foo', mismatch between port which is an interface array of size 6, and expression which is an interface array of size 5.
+q{%Error: t/t_interface_size_bad.v:\d+: Illegal IFACEREF port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 4.
+%Error: t/t_interface_size_bad.v:\d+: Illegal IFACEREF port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 6.
 %Error: Exiting due to.*},
     );
 

test_regress/t/t_interface_star.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_interface_star.v

@@ -0,0 +1,41 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   integer cyc=1;
+
+   counter_io c_data();
+
+   counter_ansi c1 (.clk, .*);
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc==20) begin
+	 if (c_data.value != 12345) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+endmodule
+
+interface counter_io;
+  integer value;
+endinterface
+
+module counter_ansi
+  (
+   input clk,
+   counter_io c_data
+   );
+
+   always_ff @ (posedge clk) begin
+      c_data.value <= 12345;
+   end
+endmodule : counter_ansi

test_regress/t/t_lint_literal_bad.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2017 by Todd Strader. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->skip("Verilator only test") if !$Self->{vlt};
+
+compile (
+	 fails=>1,
+	 expect=>
+'%Warning-WIDTH: t/t_lint_literal_bad.v:9: Value too large for 8 bit number: 256
+',
+	 );
+
+ok(1);
+1;

test_regress/t/t_lint_literal_bad.v

@@ -0,0 +1,11 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Todd Strader.
+
+module t (
+);
+
+    localparam the_localparam = 8'd256;
+
+endmodule

test_regress/t/t_math_pow5.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_math_pow5.v

@@ -0,0 +1,73 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2004 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   reg [67:0] q;
+   reg signed [67:0] qs;
+
+   initial begin
+      q = 68'he_12345678_9abcdef0 ** 68'h3;
+      if (q != 68'hcee3cb96ce96cf000) $stop;
+      //
+      q = 68'he_12345678_9abcdef0 ** 68'h5_6789abcd_ef012345;
+      if (q != 68'h0) $stop;
+      //
+      qs = 68'she_12345678_9abcdef0 ** 68'sh3;
+      if (qs != 68'shcee3cb96ce96cf000) $stop;
+      //
+      qs = 68'she_12345678_9abcdef0 ** 68'sh5_6789abcd_ef012345;
+      if (qs != 68'h0) $stop;
+   end
+   
+   reg [67:0] left;
+   reg [67:0] right;
+
+   wire [67:0] outu = left ** right;
+   wire signed [67:0] outs = $signed(left) ** $signed(right);
+
+   integer cyc; initial cyc=1;
+   always @ (posedge clk) begin
+      if (cyc!=0) begin
+	 cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
+	 $write("%d %x %x %x %x\n", cyc, left, right, outu, outs);
+`endif
+	 if (cyc==1) begin
+	    left <= 68'h1;
+	    right <= '0;
+	 end
+	 if (cyc==2) begin
+	    if (outu  != 68'h1) $stop;
+	    if (outs  != 68'h1) $stop;
+	 end
+	 if (cyc==3) begin
+	    left <= 68'he_12345678_9abcdef0;
+	    right <= 68'h3;
+	 end
+	 if (cyc==4) begin
+	    if (outu != 68'hcee3cb96ce96cf000) $stop;
+	    if (outs != 68'hcee3cb96ce96cf000) $stop;
+	 end
+	 if (cyc==5) begin
+	    left <= 68'he_12345678_9abcdef0;
+	    right <= 68'h5_6789abcd_ef012345;
+	 end
+	 if (cyc==6) begin
+	    if (outu != 68'h0) $stop;
+	    if (outs != 68'h0) $stop;
+	 end
+	 if (cyc==9) begin
+	    $write("*-* All Finished *-*\n");
+	    $finish;
+	 end
+      end
+   end
+endmodule

test_regress/t/t_math_shift.v

@@ -5,17 +5,24 @@
 
 module t (/*AUTOARG*/
    // Outputs
-   ign,
+   ign, ign2, ign3,
    // Inputs
    clk
    );
 
    input clk;
    output [31:0] ign;
+   output [3:0]  ign2;
+   output [11:0]  ign3;
 
    parameter [95:0] P6 = 6;
    localparam P64 = (1 << P6);
 
+   // verilator lint_off WIDTH
+   localparam [4:0] PBIG23 = 1'b1 << ~73'b0;
+   localparam [3:0] PBIG29 = 4'b1 << 33'h100000000;
+   // verilator lint_on WIDTH
+
    reg [31:0] 		right;
    reg [31:0] 		left;
    reg [P64-1:0] 	qright;
@@ -23,6 +30,14 @@ module t (/*AUTOARG*/
    reg [31:0] 		amt;
 
    assign ign = {31'h0, clk} >>> 4'bx;  // bug760
+   assign ign2 = {amt[1:0] >> {22{amt[5:2]}}, amt[1:0] << (0 <<< amt[5:2])}; // bug1174
+   assign ign3 = {amt[1:0] >> {22{amt[5:2]}},
+		  amt[1:0] >> {11{amt[5:2]}},
+		  $signed(amt[1:0]) >>> {22{amt[5:2]}},
+		  $signed(amt[1:0]) >>> {11{amt[5:2]}},
+		  amt[1:0] << {22{amt[5:2]}},
+                  amt[1:0] << {11{amt[5:2]}}};
+
 
    always @* begin
       right = 32'h819b018a >> amt;

test_regress/t/t_math_signed5.v

@@ -83,6 +83,7 @@
       w4_u = ((5'b01010 == (5'sb11111 / 5'sd3)));    // Exp 0     Vlt 0  // Must be signed result (-1/3) to make this result zero
 `ifdef VCS  // I-2014.03
       `checkh(w4_u, 4'b0000);  // Wrong, gets 5'b0==..., unsigned does not propagate
+      // Somewhat questionable, as spec says division signed depends on only LHS and RHS, however differs from others
 `else
       `checkh(w4_u, 4'b0001);  // NC-Verilog, Modelsim, XSim, ...
 `endif

test_regress/t/t_mem_banks.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_mem_banks.v

@@ -0,0 +1,72 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+
+   reg [5:0] 	addr;
+
+   parameter BANKS = 6;
+   parameter ROWS = 8;
+
+   wire [2:0]	bank;
+   wire [2:0]	row;
+
+   integer 	a;
+   integer 	used[BANKS][ROWS];
+
+   // Test loop
+   initial begin
+      for (a = 0; a < BANKS*ROWS; ++a) begin
+	 addr[5:0] = a[5:0];
+	 hash (addr, bank, row);
+	 used [bank][row] ++;
+	 if (used [bank][row] > 1) begin
+	    $write ("Error: Hash failed addr=%x bank=%x row=%x\n", addr, bank, row);
+	 end
+      end
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+   task hash (input [5:0] addr,
+	      output [2:0] bank,
+	      output [2:0] row);
+
+      reg [1:0] third;
+      reg [1:0] fourth;
+
+      third = {addr[5], addr[4]};
+      fourth = {addr[3] ^ addr[1],
+		addr[2] ^ addr[0]};
+
+      case (third)
+	2'h0:
+	  case (fourth)
+	    2'h0: begin bank = 3'h0; row = {1'h0, addr[1:0]}; end
+	    2'h1: begin bank = 3'h1; row = {1'h0, addr[1:0]}; end
+	    2'h2: begin bank = 3'h2; row = {1'h0, addr[1:0]}; end
+	    2'h3: begin bank = 3'h3; row = {1'h0, addr[1:0]}; end
+	  endcase
+
+	2'h1:
+	  case (fourth)
+	    2'h0: begin bank = 3'h0; row = {1'h1, addr[1:0]}; end
+	    2'h1: begin bank = 3'h1; row = {1'h1, addr[1:0]}; end
+	    2'h2: begin bank = 3'h4; row = {1'h0, addr[1:0]}; end
+	    2'h3: begin bank = 3'h5; row = {1'h0, addr[1:0]}; end
+	  endcase
+
+	2'h2:
+	  case (fourth)
+	    2'h0: begin bank = 3'h2; row = {1'h1, addr[1:0]}; end
+	    2'h1: begin bank = 3'h3; row = {1'h1, addr[1:0]}; end
+	    2'h2: begin bank = 3'h4; row = {1'h1, addr[1:0]}; end
+	    2'h3: begin bank = 3'h5; row = {1'h1, addr[1:0]}; end
+	  endcase
+
+	2'h3: $stop;
+      endcase
+   endtask
+endmodule

test_regress/t/t_param_array2.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_param_array2.v

@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Wilson Snyder.
+
+module t;
+   localparam int c[4] = '{5, 6, 7, 8};
+   a #(.p(c)) i_a ();
+endmodule
+
+module a
+  #( parameter int p[4] = '{1, 2, 3, 4} );
+   initial begin
+      if (p[0] != 5) $stop;
+      if (p[1] != 6) $stop;
+      if (p[2] != 7) $stop;
+      if (p[3] != 8) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

test_regress/t/t_sys_plusargs.v

@@ -8,6 +8,8 @@ module t;
    integer p_i;
    reg [7*8:1] p_str;
    string      sv_str;
+   reg [7*8:1] p_in;
+   string      sv_in;
 
    initial begin
       if ($test$plusargs("PLUS")!==1) $stop;
@@ -20,23 +22,47 @@ module t;
       if ($value$plusargs("NOTTHERE%d", p_i)!==0) $stop;
       if (p_i !== 10) $stop;
 
+      p_i = 0;
       if ($value$plusargs("INT=%d", p_i)!==1) $stop;
       if (p_i !== 32'd1234) $stop;
 
+      p_i = 0;
       if ($value$plusargs("INT=%H", p_i)!==1) $stop;  // tests uppercase % also
       if (p_i !== 32'h1234) $stop;
 
-      if ($value$plusargs("INT=%o", p_i)!==1) $stop;
+      p_i = 0;
+      // Check octal and WIDTH
+      if (!$value$plusargs("INT=%o", p_i)) $stop;
       if (p_i !== 32'o1234) $stop;
 
+      p_str = "none";
       if ($value$plusargs("IN%s", p_str)!==1) $stop;
       $display("str='%s'",p_str);
       if (p_str !== "T=1234") $stop;
 
+      sv_str = "none";
       if ($value$plusargs("IN%s", sv_str)!==1) $stop;
       $display("str='%s'",sv_str);
       if (sv_str != "T=1234") $stop;
 
+      p_in = "IN%s";
+`ifdef VERILATOR
+      p_in = $c(p_in); // Prevent constant propagation
+`endif
+      sv_str = "none";
+      if ($value$plusargs(p_in, sv_str)!==1) $stop;
+      $display("str='%s'",sv_str);
+      if (sv_str != "T=1234") $stop;
+
+      sv_in = "INT=%d";
+`ifdef VERILATOR
+      if ($c1(0)) sv_in = "NEVER"; // Prevent constant propagation
+`endif
+      p_i = 0;
+      if ($value$plusargs(sv_in, p_i)!==1) $stop;
+      $display("i='%d'",p_i);
+      if (p_i !== 32'd1234) $stop;
+
       $write("*-* All Finished *-*\n");
       $finish;
    end

test_regress/t/t_sys_plusargs_bad.pl

@@ -8,13 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 
 compile (
-	 fails=>$Self->{v3},
-	 expect=>
-q{%Error: t/t_sys_plusargs_bad.v:\d+: Missing or extra \$value\$plusargs format qualifier: 'NOTTHERE'
-%Error: t/t_sys_plusargs_bad.v:\d+: Illegal \$value\$plusargs format qualifier: 'z'
-%Error: t/t_sys_plusargs_bad.v:\d+: Missing or extra \$value\$plusargs format qualifier: 'INT=%x%x'
-%Error: Exiting due to.*},
-	 );
+    );
+
+execute (
+    check_finished=>1,
+    );
 
 ok(1);
 1;