Version bump

Changes

@@ -3,6 +3,26 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.714 2009/09/18
+
+**   Add --bbox-sys option to blackbox $system calls.
+
+**   Support generate for var++, var--, ++var, --var.
+
+***  Improved warning when "do" used as identifier.
+
+**** Don't require SYSTEMPERL_INCLUDE if SYSTEMPERL/src exists. [Gary Thomas]
+
+**** Fix deep defines causing flex scanner overflows. [Brad Dobbie]
+
+**** Fix preprocessing commas in deep parameterized macros. [Brad Dobbie]
+
+**** Fix tracing escaped dotted identifiers, bug107.
+
+**** Fix $display with uppercase %M.
+
+**** Fix --error-limit option being ignored.
+
 * Verilator 3.713 2009/08/04
 
 **   Support constant function calls for parameters. [many!]

bin/verilator

@@ -179,6 +179,7 @@ descriptions in the next sections for more information.
 
     --assert                    Enable all assertions
     --autoflush                 Flush streams after all $displays
+    --bbox-sys                  Blackbox unknown $system calls
     --bin <filename>            Override Verilator binary
     --cc                        Create C++ output
     --compiler <compiler-name>  Tune for specified C++ compiler
@@ -193,7 +194,7 @@ descriptions in the next sections for more information.
     --debugi-<srcfile> <level>  Enable debugging a source file at a level
     --dump-tree                 Enable dumping .tree files
     -E                          Preprocess, but do not compile
-    --error-limit <value>	Abort after this number of errors
+    --error-limit <value>       Abort after this number of errors
     --exe                       Link to create executable
     -f <file>                   Parse options from a file
     --help                      Display this help.
@@ -228,11 +229,14 @@ descriptions in the next sections for more information.
     --trace-depth <levels>      Depth of tracing
     -U<var>                     Undefine preprocessor define
     --underline-zero            Zero signals with leading _'s
-    -V				Verbose version and config
+    --unroll-count <loops>      Tune maximum loop iterations
+    --unroll-stmts <stmts>      Tune maximum loop body size
+    -V                          Verbose version and config
     -v <filename>               Verilog library
     -Werror-<message>           Convert warning to error
     -Wfuture-<message>          Disable unknown message warnings
     -Wno-<message>              Disable warning
+    -Wno-lint                   Disable all lint warnings
     -x-assign <mode>            Initially assign Xs to this value
     -y <dir>                    Directory to search for modules
 
@@ -269,6 +273,14 @@ After every $display or $fdisplay, flush the output stream.  This insures
 that messages will appear immediately but may reduce performance.  Defaults
 off, which will buffer output as provided by the normal C stdio calls.
 
+=item --bbox-sys
+
+Black box any unknown $system task or function calls.  System tasks will be
+simply NOPed, and system functions will be replaced by unsized zero.
+Arguments to such functions will be parsed, but not otherwise checked.
+This prevents errors when linting in the presence of company specific PLI
+calls.
+
 =item --bin I<filename>
 
 Rarely needed.  Override the default filename for Verilator itself.  When a
@@ -441,6 +453,9 @@ appropriate `begin_keywords.
 
 Check the files for lint violations only, do not create any other output.
 
+If the design is not to be completely Verilated see also the --bbox-sys
+option.
+
 =item --MMD
 
 Enable creation of .d dependency files, used for make dependency detection,
@@ -610,6 +625,16 @@ zero, as was done in Verilator 2.  Default is for all signals including
 those with underlines being randomized.  This option may be depreciated in
 future versions.
 
+=item --unroll-count I<loops>
+
+Rarely needed.  Specifies the maximum number of loop iterations that may be
+unrolled.  See also BLKLOOPINIT warning.
+
+=item --unroll-stmts I<statements>
+
+Rarely needed.  Specifies the maximum number of statements in a loop for
+that loop to be unrolled. See also BLKLOOPINIT warning.
+
 =item -Werror-I<message>
 
 Convert the specified warning message into a error message.  This is
@@ -1816,7 +1841,8 @@ it's a bit slower than a non-delayed assignment.)  Here's an example
 
 This message is only seen on large or complicated loops because Verilator
 generally unrolls small loops.  You may want to try increasing
---unroll-count which will raise the small loop bar to avoid this error.
+--unroll-count (and occasionally --unroll-stmts) which will raise the small
+loop bar to avoid this error.
 
 =item CASEINCOMPLETE
 
@@ -2253,6 +2279,9 @@ see below and the test_c/sim_main.cpp file of the distribution.
 You also need to compile SpTraceVcdC.cpp and add it to your link.  This is
 done for you if using the Verilator --exe flag.
 
+Note you can also call ->trace on multiple Verilated objects with the same
+trace file if you want all data to land in the same output file.
+
     #include "SpTraceVcdC.cpp"
     ...
     int main(int argc, char **argv, char **env) {
@@ -2283,12 +2312,18 @@ Alternatively you may use the C++ trace mechanism described in the previous
 question, however the timescale and timeprecision will not inherited from
 your SystemC settings.
 
+You'll then need to compile in Sp.cpp, which includes SpTraceVcd.cpp among
+other things.
+
+Note you can also call ->trace on multiple Verilated objects with the same
+trace file if you want all data to land in the same output file.
+
     #include "SpTraceVcd.cpp"
     ...
     int main(int argc, char **argv, char **env) {
         ...
         Verilated::traceEverOn(true);
-        SpTraceVcdFile* tfp = new SpTraceVcdFile;
+        SpTraceFile* tfp = new SpTraceFile;
         topp->trace (tfp, 99);
         tfp->open ("obj_dir/t_trace_ena_cc/simx.vcd");
         ...

src/V3Assert.cpp

@@ -65,7 +65,9 @@ private:
 	AstNode* timesp = nodep->exprsp(); if (timesp) timesp->unlinkFrBack();
 	timesp = timesp->addNext(new AstTime(nodep->fileline()));
 	nodep->exprsp(timesp);
-	if (!nodep->scopeNamep() && nodep->name().find("%m") != string::npos) {
+	if (!nodep->scopeNamep()
+	    && (nodep->name().find("%m") != string::npos
+		|| nodep->name().find("%M") != string::npos)) {
 	    nodep->scopeNamep(new AstScopeName(nodep->fileline()));
 	}
     }

src/V3Const.cpp

@@ -313,15 +313,24 @@ private:
 	    if (m_warn
 		&& nodep->lsbp()->castConst()
 		&& nodep->widthp()->castConst()
-		&& (!varp->rangep() || varp->msb())  // else it's non-resolvable parameterized
-		&& ( (  (nodep->msbConst() > varp->msbMaxSelect())
-			|| (nodep->lsbConst() > varp->msbMaxSelect())))) {
-		// See also warning in V3Width
-		nodep->v3error("Selection index out of range: "
-			       <<nodep->msbConst()<<":"<<nodep->lsbConst()
-			       <<" outside "<<varp->msbMaxSelect()<<":0"
-			       <<(varp->lsb()>=0 ? ""
-				  :" (adjusted +"+cvtToStr(-varp->lsb())+" to account for negative lsb)"));
+		&& (!varp->rangep() || varp->msb())) {  // else it's non-resolvable parameterized
+		if (nodep->lsbp()->castConst()->num().isFourState()
+		    || nodep->widthp()->castConst()->num().isFourState()) {
+		    nodep->v3error("Selection index is constantly unknown or tristated: "
+				   "lsb="<<nodep->lsbp()->name()<<" width="<<nodep->widthp()->name());
+		    // Replacing nodep will make a mess above, so we replace the offender
+		    replaceZero(nodep->lsbp());
+		}
+		else if ((nodep->msbConst() > varp->msbMaxSelect())
+			 || (nodep->lsbConst() > varp->msbMaxSelect())) {
+		    // See also warning in V3Width
+		    nodep->v3error("Selection index out of range: "
+				   <<nodep->msbConst()<<":"<<nodep->lsbConst()
+				   <<" outside "<<varp->msbMaxSelect()<<":0"
+				   <<(varp->lsb()>=0 ? ""
+				      :" (adjusted +"+cvtToStr(-varp->lsb())+" to account for negative lsb)"));
+		    // Don't replace with zero, we'll do it later
+		}
 	    }
 	}
 	return false;  // Not a transform, so NOP
@@ -367,7 +376,9 @@ private:
     void replaceNum (AstNode* oldp, const V3Number& num) {
 	// Replace oldp node with a constant set to specified value
 	UASSERT (oldp, "Null old\n");
-	if (oldp->castConst()) oldp->v3fatalSrc("Already constant??\n");
+	if (oldp->castConst() && !oldp->castConst()->num().isFourState()) {
+	    oldp->v3fatalSrc("Already constant??\n");
+	}
 	AstNode* newp = new AstConst(oldp->fileline(), num);
 	newp->widthSignedFrom(oldp);
 	if (debug()>5) oldp->dumpTree(cout,"  const_old: ");

src/V3EmitC.cpp

@@ -1796,10 +1796,13 @@ class EmitCTrace : EmitCStmts {
 	puts("if (!Verilated::calcUnusedSigs()) vl_fatal(__FILE__,__LINE__,__FILE__,\"Turning on wave traces requires Verilated::traceEverOn(true) call before time 0.\");\n");
 
 	//Future; need to wait to estabilish backwards compatibility
-	//puts("#if defined(SPTRACEVCDC_VERSION) && SPTRACEVCDC_VERSION >= 1320\n");
-	//puts("vcdp->scopeEscape(' ');\n");
+	puts("#if defined(SPTRACEVCDC_VERSION) && SPTRACEVCDC_VERSION >= 1330\n");
+	puts("vcdp->scopeEscape(' ');\n");
 	puts("t->traceInitThis (vlSymsp, vcdp, code);\n");
-	//puts("vcdp->scopeEscape('.');\n");  // Restore so SystemPerl traced files won't break
+	puts("vcdp->scopeEscape('.');\n");  // Restore so SystemPerl traced files won't break
+	puts("#else\n");
+	puts("t->traceInitThis (vlSymsp, vcdp, code);\n");
+	puts("#endif\n");
 	puts("}\n");
 
 	puts("void "+topClassName()+"::traceFull(SpTraceVcd* vcdp, void* userthis, uint32_t code) {\n");

src/V3LinkResolve.cpp

@@ -361,7 +361,7 @@ private:
 		inPct = true;
 	    } else if (inPct) {
 		inPct = false;
-		switch (ch) {
+		switch (tolower(ch)) {
 		case '0': case '1': case '2': case '3': case '4':
 		case '5': case '6': case '7': case '8': case '9':
 		    inPct = true;
@@ -441,7 +441,8 @@ private:
 	    nodep->v3error(nodep->verilogKwd()+" only allowed under a assertion.");
 	}
 	if (nodep->displayType().needScopeTracking()
-	    || nodep->name().find("%m") != string::npos) {
+	    || nodep->name().find("%m") != string::npos
+	    || nodep->name().find("%M") != string::npos) {
 	    nodep->scopeNamep(new AstScopeName(nodep->fileline()));
 	}
     }

src/V3Options.cpp

@@ -374,27 +374,27 @@ string V3Options::getenvSYSTEMPERLGuts() {
 
 string V3Options::getenvSYSTEMPERL_INCLUDE() {
     string var = getenvStr("SYSTEMPERL_INCLUDE","");
-    if (var == "" && string(DEFENV_SYSTEMPERL_INCLUDE) != "") {
-	// Note if SYSTEMPERL is DEFENVed, then SYSTEMPERL_INCLUDE is also DEFENVed
-	// So we don't need to sweat testing SYSTEMPERL also
-	var = DEFENV_SYSTEMPERL_INCLUDE;
-	setenvStr("SYSTEMPERL_INCLUDE", var, "Hardcoded at build time");
+    if (var == "") {
+	string sp_src = V3Options::getenvSYSTEMPERLGuts()+"/src";
+	if (V3Options::fileStatNormal(sp_src+"/systemperl.h")) {
+ 	    var = sp_src;
+	    setenvStr ("SYSTEMPERL_INCLUDE", var, "From $SYSTEMPERL/src");
+	} else if (string(DEFENV_SYSTEMPERL_INCLUDE) != "") {
+	    // Note if SYSTEMPERL is DEFENVed, then SYSTEMPERL_INCLUDE is also DEFENVed
+	    // So we don't need to sweat testing DEFENV_SYSTEMPERL also
+	    var = DEFENV_SYSTEMPERL_INCLUDE;
+	    setenvStr("SYSTEMPERL_INCLUDE", var, "Hardcoded at build time");
+	}
     }
     // Only correct or check it if we really need the value
     if (v3Global.opt.usingSystemPerlLibs()) {
-	if (var == "") {
-	    string sp = V3Options::getenvSYSTEMPERLGuts();
-	    var = sp+"/src";
-	    setenvStr ("SYSTEMPERL_INCLUDE", var, "From $SYSTEMPERL/src");
-	}
 	// We warn about $SYSTEMPERL instead of _INCLUDE since that's more likely
 	// what users will want to set.
 	if (var == "") {
-	    v3fatal("Need $SYSTEMPERL in environment for --sp or --trace\n"
+	    v3fatal("Need $SYSTEMPERL and $SYSTEMPERL_INCLUDE in environment for --sp or --trace\n"
 		    "Probably System-Perl isn't installed, see http://www.veripool.org/systemperl\n");
 	}
-	if (var != ""
-	    && !V3Options::fileStatNormal(var+"/systemperl.h")) {
+	else if (var != "" && !V3Options::fileStatNormal(var+"/systemperl.h")) {
 	    v3fatal("Neither $SYSTEMPERL nor $SYSTEMPERL_INCLUDE environment vars to point to System-Perl kit: "<<var<<endl);
 	}
     }
@@ -577,7 +577,7 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 	    }
 	    else if ( !strcmp (sw, "-error-limit") ) {
 		shift;
-		m_inlineMult = atoi(argv[i]);
+		m_errorLimit = atoi(argv[i]);
 	    }
 	    else if ( !strcmp (sw, "-inline-mult") ) {
 		shift;
@@ -638,6 +638,7 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 	    else if ( onoff   (sw, "-MP", flag/*ref*/) )	{ m_makePhony = flag; }
 	    else if ( onoff   (sw, "-assert", flag/*ref*/) )	{ m_assert = flag; m_psl = flag; }
 	    else if ( onoff   (sw, "-autoflush", flag/*ref*/) )	{ m_autoflush = flag; }
+	    else if ( onoff   (sw, "-bbox-sys", flag/*ref*/) )	{ m_bboxSys = flag; }
 	    else if ( !strcmp (sw, "-cc") )			{ m_outFormatOk = true; m_systemC = false; m_systemPerl = false; }
 	    else if ( onoff   (sw, "-coverage", flag/*ref*/) )	{ coverage(flag); }
 	    else if ( onoff   (sw, "-coverage-line", flag/*ref*/) ){ m_coverageLine = flag; }

src/V3Options.h

@@ -94,6 +94,7 @@ class V3Options {
     bool	m_makePhony;	// main switch: -MP
     bool	m_assert;	// main switch: --assert
     bool	m_autoflush;	// main switch: --autoflush
+    bool	m_bboxSys;	// main switch: --bbox-sys
     bool	m_coverageLine;	// main switch: --coverage-block
     bool	m_coverageToggle;// main switch: --coverage-toggle
     bool	m_coverageUser;	// main switch: --coverage-func
@@ -204,6 +205,7 @@ class V3Options {
     bool stats() const { return m_stats; }
     bool assertOn() const { return m_assert; }  // assertOn as __FILE__ may be defined
     bool autoflush() const { return m_autoflush; }
+    bool bboxSys() const { return m_bboxSys; }
     bool coverage() const { return m_coverageLine || m_coverageToggle || m_coverageUser; }
     bool coverageLine() const { return m_coverageLine; }
     bool coverageToggle() const { return m_coverageToggle; }

src/V3PreLex.h

@@ -26,6 +26,8 @@
 #ifndef _VPREPROCLEX_H_		// Guard
 #define _VPREPROCLEX_H_ 1
 
+#include <stack>
+
 #include "V3Error.h"
 
 // Token codes
@@ -105,7 +107,7 @@ class V3PreLex {
 
     // Parse state
     FILE*	m_fp;		// File state is for
-    YY_BUFFER_STATE  m_yyState;	// flex input state
+    stack<YY_BUFFER_STATE> m_bufferStack; // Stack of inserted text above current point
 
     // State to lexer
     static V3PreLex* s_currentLexp;	// Current lexing point
@@ -121,14 +123,18 @@ class V3PreLex {
     // CONSTRUCTORS
     V3PreLex(FILE* fp) {
 	m_fp = fp;
-	m_yyState = yy_create_buffer (fp, YY_BUF_SIZE);
 	m_keepComments = 0;
 	m_pedantic = false;
 	m_parenLevel = 0;
 	m_pslParenLevel = 0;
 	m_pslMoreNeeded = false;
+	m_bufferStack.push(yy_create_buffer (fp, YY_BUF_SIZE));
+	yy_switch_to_buffer(m_bufferStack.top());
+    }
+    ~V3PreLex() {
+	fclose(m_fp);
+	while (!m_bufferStack.empty()) { yy_delete_buffer(m_bufferStack.top()); m_bufferStack.pop(); }
     }
-    ~V3PreLex() { fclose(m_fp); yy_delete_buffer(m_yyState); }
 
     // Called by V3PreLex.l from lexer
     void appendDefValue(const char* text, int len);
@@ -139,9 +145,11 @@ class V3PreLex {
     void pushStateDefForm();
     void pushStateDefValue();
     void pushStateIncFilename();
-    void unputString(const char* textp);
+    void scanBytes(const string& strg);
     /// Called by VPreproc.cpp to get data from lexer
+    YY_BUFFER_STATE currentBuffer();
     int	 currentStartState();
+    void dumpStack();
 };
 
 #endif // Guard

src/V3PreLex.l

@@ -1,4 +1,3 @@
-/* -*- C++ -*- */
 /**************************************************************************
  * DESCRIPTION: Verilator: Flex verilog preprocessor
  *
@@ -131,6 +130,7 @@ psl		[p]sl
 	/* Note '(' must IMMEDIATELY follow definition name */
 <DEFFPAR>[(]		{ appendDefValue("(",1); BEGIN(DEFFORM); }
 <DEFFPAR>{crnl}		{ yy_pop_state(); unput('\n'); yyleng=0; return VP_DEFFORM; } /* DEFVAL will later grab the return */
+<DEFFPAR><<EOF>>	{ yy_pop_state(); return VP_DEFFORM; }  /* empty formals */
 <DEFFPAR>.		{ yy_pop_state(); unput(yytext[yyleng-1]); yyleng=0; return VP_DEFFORM; }  /* empty formals */
  
 	/* Reading definition formals */
@@ -204,7 +204,6 @@ psl		[p]sl
 <PSLONEM>[{(]		{ pslParenLevelInc(); return (VP_TEXT); }
 <PSLONEM>[})]		{ pslParenLevelDec(); return (VP_TEXT); }
 <PSLONEM>[;]		{ if (!pslParenLevel()) {BEGIN PSLONEE; pslMoreNeeded(false);} return (VP_TEXT); }
-<PSLONEM><<EOF>>	{ yyerrorf("EOF in '/* ... */' psl comment\n"); yyleng=0; yyterminate(); }
 <PSLONEM>{crnl}		{ linenoInc(); yy_pop_state(); yytext=(char*)"\n"; yyleng=1; return(VP_WHITE); }
 
 	/* Completed psl oneline comments */
@@ -224,16 +223,17 @@ psl		[p]sl
 <CMTMODE>.			{ yymore(); }
 
 	/* Psl C-style comments. */
+	/* EOFs are normal because / * `foo(..) * / hits a unputString EOF */
 <PSLMUL1>.|{crnl}	{ yyless(0); BEGIN PSLMULM; return(VP_PSL); }
 <PSLMULM>"*/"		{ yy_pop_state(); return(VP_COMMENT); }
 <PSLMULM>"//"[^\n\r]*	{ return (VP_COMMENT); }	/* Comments inside block comments get literal inclusion (later removal) */
-<PSLMULM><<EOF>>	{ yyerrorf("EOF in '/* ... */' psl comment\n"); yyleng=0; yyterminate(); }
 
 	/* Define calls */
 <INITIAL,PSLMULM,PSLONEM>"`"{symb}	{ return (VP_DEFREF); }
 
 	/* Generics */
 <INITIAL,PSLMULM>{crnl}		{ linenoInc(); yytext=(char*)"\n"; yyleng=1; return(VP_WHITE); }
+<INITIAL,PSLMULM,PSLONEM><<EOF>> { yyterminate(); }  /* A "normal" EOF */
 <INITIAL,PSLMULM,PSLONEM>{symb}	{ return (VP_SYMBOL); }
 <INITIAL,PSLMULM,PSLONEM>{wsn}+	{ return (VP_WHITE); }
 <INITIAL,PSLMULM,PSLONEM>{drop}	{ }
@@ -268,13 +268,9 @@ void V3PreLex::pushStateIncFilename() {
     yymore();
 }
 
-void V3PreLex::unputString(const char* textp) {
-    // Add characters to input stream in back-to-front order
-    const char* cp;
-    for (cp = textp; *cp; cp++);
-    for (cp--; cp >= textp; cp--) {
-	unput(*cp);
-    }
+void V3PreLex::scanBytes(const string& strg) {
+    yy_scan_bytes(strg.c_str(), strg.length());
+    m_bufferStack.push(currentBuffer());  // yy_scan_bytes makes new buffer
 }
 
 void V3PreLex::appendDefValue(const char* textp, int len) {
@@ -282,6 +278,10 @@ void V3PreLex::appendDefValue(const char* textp, int len) {
     m_defValue.append(textp,len);
 }
 
+YY_BUFFER_STATE V3PreLex::currentBuffer() {
+    return YY_CURRENT_BUFFER;
+}
+
 int V3PreLex::currentStartState() {
     return YY_START;
 }
@@ -291,3 +291,20 @@ void V3PreLex::lineDirective(const char* textp) {
     // Make sure we have a dependency on whatever file was specified
     V3File::addSrcDepend(m_curFilelinep->filename());
 }
+
+void V3PreLex::dumpStack() {
+    // For debug use
+    stack<YY_BUFFER_STATE> tmpstack = m_bufferStack;
+    printf("  bufferStack[%p]:",this);
+    while (!tmpstack.empty()) {
+	printf(" %p",tmpstack.top());
+	tmpstack.pop();
+    }
+    printf("\n");
+}
+ 
+/*###################################################################
+ * Local Variables:
+ * mode: C++
+ * End:
+ */

src/V3PreProc.cpp

@@ -160,6 +160,7 @@ private:
 
     bool commentTokenMatch(string& cmdr, const char* strg);
     string trimWhitespace(const string& strg);
+    void unputString(const string& strg);
 
     void parsingOn() {
 	m_off--;
@@ -386,6 +387,18 @@ const char* V3PreProcImp::tokenName(int tok) {
     }
 }
 
+void V3PreProcImp::unputString(const string& strg) {
+    // We used to just m_lexp->unputString(strg.c_str());
+    // However this can lead to "flex scanner push-back overflow"
+    // so instead we scan from a temporary buffer, then on EOF return.
+    // This is also faster than the old scheme, amazingly.
+    if (m_lexp->m_bufferStack.empty() || m_lexp->m_bufferStack.top()!=m_lexp->currentBuffer()) {
+	fileline()->v3fatalSrc("bufferStack missing current buffer; will return incorrectly");
+	// Hard to debug lost text as won't know till much later
+    }
+    m_lexp->scanBytes(strg);
+}
+
 string V3PreProcImp::trimWhitespace(const string& strg) {
     string out = strg;
     while (out.length()>0 && isspace(out[0])) {
@@ -535,7 +548,6 @@ void V3PreProcImp::openFile(FileLine* fl, const string& filename) {
     addLineComment(1); // Enter
 
     yy_flex_debug = (debug()>4)?1:0;
-    yy_switch_to_buffer(m_lexp->m_yyState);
 }
 
 void V3PreProcImp::insertUnreadbackAtBol(const string& text) {
@@ -560,16 +572,27 @@ void V3PreProcImp::addLineComment(int enter_exit_level) {
 }
 
 void V3PreProcImp::eof() {
-    // Remove current lexer
-    UINFO(4,fileline()<<"EOF!\n");
-    addLineComment(2);	// Exit
-    delete m_lexp;  m_lexp=NULL;
-    // Perhaps there's a parent file including us?
-    if (!m_includeStack.empty()) {
-	// Back to parent.
-	m_lexp = m_includeStack.top(); m_includeStack.pop();
-	addLineComment(0);
-	yy_switch_to_buffer(m_lexp->m_yyState);
+    // Perhaps we're completing unputString
+    if (m_lexp->m_bufferStack.size()>1) {
+	UINFO(4,fileline()<<"EOS\n");
+	// Switch to file or next unputString, but not a eof so don't delete lexer
+	yy_delete_buffer(m_lexp->currentBuffer());
+	m_lexp->m_bufferStack.pop();  // Must work as size>1
+	yy_switch_to_buffer(m_lexp->m_bufferStack.top());
+    } else {
+	// Remove current lexer
+	UINFO(4,fileline()<<"EOF!\n");
+	addLineComment(2);	// Exit
+	// Destructor will call yy_delete_buffer
+	delete m_lexp;  m_lexp=NULL;
+	// Perhaps there's a parent file including us?
+	if (!m_includeStack.empty()) {
+	    // Back to parent.
+	    m_lexp = m_includeStack.top(); m_includeStack.pop();
+	    addLineComment(0);
+	    if (m_lexp->m_bufferStack.empty()) fileline()->v3fatalSrc("No include buffer to return to");
+	    yy_switch_to_buffer(m_lexp->m_bufferStack.top());  // newest buffer in older lexer
+	}
     }
 }
 
@@ -794,6 +817,7 @@ int V3PreProcImp::getToken() {
 	    if (m_defRefs.empty()) v3fatalSrc("Shouldn't be in DEFARG w/o active defref");
 	    V3DefineRef* refp = &(m_defRefs.top());
 	    refp->nextarg(refp->nextarg()+m_lexp->m_defValue); m_lexp->m_defValue="";
+	    UINFO(4,"defarg++ "<<refp->nextarg()<<endl);
 	    if (tok==VP_DEFARG && yyleng==1 && yytext[0]==',') {
 		refp->args().push_back(refp->nextarg());
 		m_state = ps_DEFARG;
@@ -806,13 +830,17 @@ int V3PreProcImp::getToken() {
 		// Substitute in and prepare for next action
 		// Similar code in non-parenthesized define (Search for END_OF_DEFARG)
 		m_defRefs.pop();
-		m_lexp->unputString(out.c_str());
 		if (m_defRefs.empty()) {
+		    unputString(out.c_str());
 		    m_state = ps_TOP;
 		    m_lexp->m_parenLevel = 0;
 		}
 		else {  // Finished a defref inside a upper defref
+		    // Can't subst now, or
+		    // `define a(ign) x,y
+		    // foo(`a(ign),`b)  would break because a contains comma
 		    refp = &(m_defRefs.top());  // We popped, so new top
+		    refp->nextarg(refp->nextarg()+m_lexp->m_defValue+out); m_lexp->m_defValue="";
 		    m_lexp->m_parenLevel = refp->parenLevel();
 		    m_state = ps_DEFARG;
 		}
@@ -936,7 +964,7 @@ int V3PreProcImp::getToken() {
 			// Similar code in parenthesized define (Search for END_OF_DEFARG)
 			if (m_defRefs.empty()) {
 			    // Just output the substitution
-			    m_lexp->unputString(out.c_str());
+			    unputString(out.c_str());
 			} else {
 			    // Inside another define.  Can't subst now, or
 			    // `define a x,y

src/V3Signed.cpp

@@ -179,7 +179,7 @@ private:
 	    if (!inPct && ch=='%') {
 		inPct = true;
 	    } else if (inPct && isdigit(ch)) {
-	    } else if (inPct) {
+	    } else if (tolower(inPct)) {
 		inPct = false;
 		switch (tolower(ch)) {
 		case '%': break;  // %% - just output a %

src/V3Tristate.cpp

@@ -650,6 +650,7 @@ private:
 	    if (nodep->modVarp()->user1p()) {
 		// create the input pin
 		AstVarRef* refp = nodep->exprp()->castVarRef();
+		if (!refp) nodep->v3fatal("Unsupported: Tristate pin not connected to simple net");
 		AstVar* inp;
 		if (refp->varp()->user1p()) { // this is a tristate
 		    inp = (AstVar*) refp->varp()->user1p();

src/config_build.h.in

@@ -25,7 +25,7 @@
 //**********************************************************************
 //**** Version and host name
 
-#define DTVERSION	"Verilator 3.713 2009/08/04"
+#define DTVERSION	"Verilator 3.714 2009/09/18"
 
 //**********************************************************************
 //**** Functions

src/verilog.l

@@ -44,6 +44,10 @@ extern void yyerrorf(const char* format, ...);
 
 #define FL { yylval.fileline = CRELINE(); }
 
+#define RETURN_BBOX_SYS_OR_MSG(msg,yytext) {	\
+	if (v3Global.opt.bboxSys()) return yD_aIGNORE; \
+	else yyerrorf(msg,yytext); }
+
 void V3Read::ppline (const char* textp) {
     // Handle `line directive
     fileline()->lineDirective(textp);
@@ -239,18 +243,18 @@ escid	\\[^ \t\f\r\n]+
   "xnor"		{ FL; return yXNOR; }
   "xor"			{ FL; return yXOR; }
   /*     Special errors */
-  "$displayb"		{ yyerrorf("Unsupported: Use $display with %%b format instead: %s",yytext); }
-  "$displayh"		{ yyerrorf("Unsupported: Use $display with %%x format instead: %s",yytext); }
-  "$displayo"		{ yyerrorf("Unsupported: Use $display with %%o format instead: %s",yytext); }
-  "$fdisplayb"		{ yyerrorf("Unsupported: Use $fdisplay with %%b format instead: %s",yytext); }
-  "$fdisplayh"		{ yyerrorf("Unsupported: Use $fdisplay with %%x format instead: %s",yytext); }
-  "$fdisplayo"		{ yyerrorf("Unsupported: Use $fdisplay with %%o format instead: %s",yytext); }
-  "$fwriteb"		{ yyerrorf("Unsupported: Use $fwrite with %%b format instead: %s",yytext); }
-  "$fwriteh"		{ yyerrorf("Unsupported: Use $fwrite with %%x format instead: %s",yytext); }
-  "$fwriteo"		{ yyerrorf("Unsupported: Use $fwrite with %%o format instead: %s",yytext); }
-  "$writeb"		{ yyerrorf("Unsupported: Use $write with %%b format instead: %s",yytext); }
-  "$writeh"		{ yyerrorf("Unsupported: Use $write with %%x format instead: %s",yytext); }
-  "$writeo"		{ yyerrorf("Unsupported: Use $write with %%o format instead: %s",yytext); }
+  "$displayb"		{ RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $display with %%b format instead: %s",yytext); }
+  "$displayh"		{ RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $display with %%x format instead: %s",yytext); }
+  "$displayo"		{ RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $display with %%o format instead: %s",yytext); }
+  "$fdisplayb"		{ RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $fdisplay with %%b format instead: %s",yytext); }
+  "$fdisplayh"		{ RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $fdisplay with %%x format instead: %s",yytext); }
+  "$fdisplayo"		{ RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $fdisplay with %%o format instead: %s",yytext); }
+  "$fwriteb"		{ RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $fwrite with %%b format instead: %s",yytext); }
+  "$fwriteh"		{ RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $fwrite with %%x format instead: %s",yytext); }
+  "$fwriteo"		{ RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $fwrite with %%o format instead: %s",yytext); }
+  "$writeb"		{ RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $write with %%b format instead: %s",yytext); }
+  "$writeh"		{ RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $write with %%x format instead: %s",yytext); }
+  "$writeo"		{ RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $write with %%o format instead: %s",yytext); }
   /*     Generic unsupported warnings */
   "cmos"		{ yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
   "deassign"		{ yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
@@ -461,7 +465,7 @@ escid	\\[^ \t\f\r\n]+
 
   /* Default PLI rule */
 <V95,V01,V05,S05,PSL>{
-  "$"[a-zA-Z_$][a-zA-Z0-9_$]*	{ yyerrorf("Unsupported or unknown PLI call: %s",yytext); }
+  "$"[a-zA-Z_$][a-zA-Z0-9_$]*	{ FL; RETURN_BBOX_SYS_OR_MSG("Unsupported or unknown PLI call: %s",yytext); }
 }
 
   /************************************************************************/

src/verilog.y

@@ -113,6 +113,12 @@ static AstNode* newVarInit(FileLine* fileline, AstNode* varp, AstNode* initp) {
 
 #define INSTPREP(modname,paramsp) { V3Parse::s_impliedDecl = true; V3Parse::s_instModule = modname; V3Parse::s_instParamp = paramsp; }
 
+static void ERRSVKWD(FileLine* fileline, const string& tokname) {
+    static int toldonce = 0;
+    fileline->v3error((string)"Unexpected \""+tokname+"\": \""+tokname+"\" is a SystemVerilog keyword misused as an identifier.");
+    if (!toldonce++) fileline->v3error("Modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.");
+}
+
 //======================================================================
 
 class AstSenTree;
@@ -321,6 +327,7 @@ class AstSenTree;
 %token<fileline>	yD_UNSIGNED	"$unsigned"
 %token<fileline>	yD_WARNING	"$warning"
 %token<fileline>	yD_WRITE	"$write"
+%token<fileline>	yD_aIGNORE	"${ignored-bbox-sys}"
 
 %token<fileline>	yPSL		"psl"
 %token<fileline>	yPSL_ASSERT	"PSL assert"
@@ -657,6 +664,7 @@ port_declNetE:			// IEEE: part of port_declaration, optional net type
  
 portSig<portp>:
 		id/*port*/				{ $$ = new AstPort(CRELINE(),PINNUMINC(),*$1); }
+	|	idSVKwd					{ $$ = new AstPort(CRELINE(),PINNUMINC(),*$1); }
  	;
 
 //**********************************************************************
@@ -854,6 +862,7 @@ variable_decl_assignment<varp>:	// ==IEEE: variable_decl_assignment
 	|	id variable_dimensionListE sigAttrListE '=' variable_declExpr
 			{ $$ = VARDONEA(*$1,$2,$3);
 			  $$->addNext(new AstInitial($4,new AstAssign($4, new AstVarRef($4, *$1, true), $5))); }
+	|	idSVKwd					{ $$ = NULL; }
 	//
 	//			// IEEE: "dynamic_array_variable_identifier '[' ']' [ '=' dynamic_array_new ]"
 	//			// Matches above with variable_dimensionE = "[]"
@@ -1096,24 +1105,23 @@ genvar_initialization<nodep>:	// ==IEEE: genvar_initalization
 	;
 
 genvar_iteration<nodep>:	// ==IEEE: genvar_iteration
-		varRefBase '=' expr			{ $$ = new AstAssign($2,$1,$3); }
-	//UNSUP	id '=' 		expr			{ UNSUP }
-	//UNSUP	id yP_PLUSEQ	expr			{ UNSUP }
-	//UNSUP	id yP_MINUSEQ	expr			{ UNSUP }
-	//UNSUP	id yP_TIMESEQ	expr			{ UNSUP }
-	//UNSUP	id yP_DIVEQ	expr			{ UNSUP }
-	//UNSUP	id yP_MODEQ	expr			{ UNSUP }
-	//UNSUP	id yP_ANDEQ	expr			{ UNSUP }
-	//UNSUP	id yP_OREQ	expr			{ UNSUP }
-	//UNSUP	id yP_XOREQ	expr			{ UNSUP }
-	//UNSUP	id yP_SLEFTEQ	expr			{ UNSUP }
-	//UNSUP	id yP_SRIGHTEQ	expr			{ UNSUP }
-	//UNSUP	id yP_SSRIGHTEQ	expr			{ UNSUP }
+		varRefBase '=' 		expr		{ $$ = new AstAssign($2,$1,$3); }
+	|	varRefBase yP_PLUSEQ	expr		{ $$ = new AstAssign($2,$1,new AstAdd    ($2,$1->cloneTree(true),$3)); }
+	|	varRefBase yP_MINUSEQ	expr		{ $$ = new AstAssign($2,$1,new AstSub    ($2,$1->cloneTree(true),$3)); }
+	|	varRefBase yP_TIMESEQ	expr		{ $$ = new AstAssign($2,$1,new AstMul    ($2,$1->cloneTree(true),$3)); }
+	|	varRefBase yP_DIVEQ	expr		{ $$ = new AstAssign($2,$1,new AstDiv    ($2,$1->cloneTree(true),$3)); }
+	|	varRefBase yP_MODEQ	expr		{ $$ = new AstAssign($2,$1,new AstModDiv ($2,$1->cloneTree(true),$3)); }
+	|	varRefBase yP_ANDEQ	expr		{ $$ = new AstAssign($2,$1,new AstAnd    ($2,$1->cloneTree(true),$3)); }
+	|	varRefBase yP_OREQ	expr		{ $$ = new AstAssign($2,$1,new AstOr     ($2,$1->cloneTree(true),$3)); }
+	|	varRefBase yP_XOREQ	expr		{ $$ = new AstAssign($2,$1,new AstXor    ($2,$1->cloneTree(true),$3)); }
+	|	varRefBase yP_SLEFTEQ	expr		{ $$ = new AstAssign($2,$1,new AstShiftL ($2,$1->cloneTree(true),$3)); }
+	|	varRefBase yP_SRIGHTEQ	expr		{ $$ = new AstAssign($2,$1,new AstShiftR ($2,$1->cloneTree(true),$3)); }
+	|	varRefBase yP_SSRIGHTEQ	expr		{ $$ = new AstAssign($2,$1,new AstShiftRS($2,$1->cloneTree(true),$3)); }
 	//			// inc_or_dec_operator
-	//UNSUP	yP_PLUSPLUS id				{ UNSUP }
-	//UNSUP	yP_MINUSMINUS id			{ UNSUP }
-	//UNSUP	id yP_PLUSPLUS				{ UNSUP }
-	//UNSUP	id yP_MINUSMINUS			{ UNSUP }
+	|	yP_PLUSPLUS   varRefBase		{ $$ = new AstAssign($1,$2,new AstAdd    ($1,$2->cloneTree(true),new AstConst($1,V3Number($1,"'b1")))); }
+	|	yP_MINUSMINUS varRefBase		{ $$ = new AstAssign($1,$2,new AstSub    ($1,$2->cloneTree(true),new AstConst($1,V3Number($1,"'b1")))); }
+	|	varRefBase yP_PLUSPLUS			{ $$ = new AstAssign($2,$1,new AstAdd    ($2,$1->cloneTree(true),new AstConst($2,V3Number($2,"'b1")))); }
+	|	varRefBase yP_MINUSMINUS		{ $$ = new AstAssign($2,$1,new AstSub    ($2,$1->cloneTree(true),new AstConst($2,V3Number($2,"'b1")))); }
 	;
 
 case_generate_itemListE<nodep>:	// IEEE: [{ case_generate_itemList }]
@@ -1189,6 +1197,7 @@ netSig<varp>:			// IEEE: net_decl_assignment -  one element from list_of_port_id
 
 netId<strp>:
 		id/*new-net*/				{ $$ = $1; }
+	|	idSVKwd					{ $$ = $1; }
 	;
 
 sigId<varp>:
@@ -1315,6 +1324,7 @@ cellpinItList<pinp>:		// IEEE: list_of_port_connections + list_of_parameter_assi
 cellpinItemE<pinp>:		// IEEE: named_port_connection + named_parameter_assignment + empty
 		/* empty: ',,' is legal */		{ $$ = NULL; PINNUMINC(); }
 	|	yP_DOTSTAR				{ $$ = new AstPin($1,PINNUMINC(),".*",NULL); }
+	|	'.' idSVKwd				{ $$ = NULL; PINNUMINC(); }
 	|	'.' idAny				{ $$ = new AstPin($1,PINNUMINC(),*$2,new AstVarRef($1,*$2,false)); $$->svImplicit(true);}
 	|	'.' idAny '(' ')'			{ $$ = NULL; PINNUMINC(); }
 	|	'.' idAny '(' expr ')'			{ $$ = new AstPin($1,PINNUMINC(),*$2,$4); }
@@ -1653,7 +1663,10 @@ function_subroutine_callNoMethod<nodep>:	// IEEE: function_subroutine_call (as f
 
 system_t_call<nodep>:		// IEEE: system_tf_call (as task)
 	//
-		yD_C '(' cStrList ')'			{ $$ = (v3Global.opt.ignc() ? NULL : new AstUCStmt($1,$3)); }
+		yD_aIGNORE  '(' ')'			{ $$ = NULL; }
+	|	yD_aIGNORE  '(' exprList ')'		{ $$ = NULL; }
+	//
+	|	yD_C '(' cStrList ')'			{ $$ = (v3Global.opt.ignc() ? NULL : new AstUCStmt($1,$3)); }
 	|	yD_FCLOSE '(' idClassSel ')'		{ $$ = new AstFClose($1, $3); }
 	|	yD_FFLUSH				{ $1->v3error("Unsupported: $fflush of all handles does not map to C++.\n"); }
 	|	yD_FFLUSH '(' ')'			{ $1->v3error("Unsupported: $fflush of all handles does not map to C++.\n"); }
@@ -1687,7 +1700,10 @@ system_t_call<nodep>:		// IEEE: system_tf_call (as task)
 	;
 
 system_f_call<nodep>:		// IEEE: system_tf_call (as func)
-		yD_BITS '(' expr ')'			{ $$ = new AstAttrOf($1,AstAttrType::BITS,$3); }
+		yD_aIGNORE '(' ')'			{ $$ = new AstConst($1,V3Number($1,"'b0")); } // Unsized 0
+	|	yD_aIGNORE '(' exprList ')'		{ $$ = new AstConst($1,V3Number($1,"'b0")); } // Unsized 0
+	//
+	|	yD_BITS '(' expr ')'			{ $$ = new AstAttrOf($1,AstAttrType::BITS,$3); }
 	|	yD_C '(' cStrList ')'			{ $$ = (v3Global.opt.ignc() ? NULL : new AstUCFunc($1,$3)); }
 	|	yD_CLOG2 '(' expr ')'			{ $$ = new AstCLog2($1,$3); }
 	|	yD_COUNTONES '(' expr ')'		{ $$ = new AstCountOnes($1,$3); }
@@ -2286,6 +2302,12 @@ idAny<strp>:			// Any kind of identifier
 		yaID__ETC				{ $$ = $1; }
 	;
 
+idSVKwd<strp>:			// Warn about non-forward compatible Verilog 2001 code
+	//			// yBIT, yBYTE won't work here as causes conflicts
+		yDO					{ static string s = "do"   ; $$ = &s; ERRSVKWD($1,*$$); }
+	|	yFINAL					{ static string s = "final"; $$ = &s; ERRSVKWD($1,*$$); }
+	;
+
 variable_lvalue<nodep>:		// IEEE: variable_lvalue or net_lvalue
 	//			// Note many variable_lvalue's must use exprOkLvalue when arbitrary expressions may also exist
 		idClassSel				{ $$ = $1; }

test_regress/.gitignore

@@ -10,3 +10,4 @@ simx*
 ncverilog.*
 INCA_libs
 logs
+.vcsmx_rebuild

test_regress/Makefile

@@ -24,11 +24,13 @@ include $(VERILATOR_ROOT)/include/verilated.mk
 ######################################################################
 
 ifneq ($(VCS_HOME),)
-PRODUCTS += --vcs
+#Default to off, even with vcs; not all tests are insured to be working
+#PRODUCTS += --vcs
 endif
 
 ifneq ($(NC_ROOT),)
-PRODUCTS += --nc
+#Default to off, even with vcs; not all tests are insured to be working
+#PRODUCTS += --nc
 endif
 
 PRODUCTS += --v3

test_regress/driver.pl

@@ -236,7 +236,7 @@ sub new {
 	sim_time => 1000,
 	benchmark => $opt_benchmark,
 	# All compilers
-	v_flags => [split(/\s+/,(" -f input.vc --debug-check"
+	v_flags => [split(/\s+/,(" -f input.vc "
 				 .($opt_verbose ? " +define+TEST_VERBOSE=1":"")
 				 .($opt_benchmark ? " +define+TEST_BENCHMARK=$opt_benchmark":"")
 				 .($opt_trace ? " +define+WAVES=1":"")
@@ -245,7 +245,7 @@ sub new {
 	v_other_filenames => [],	# After the filename so we can spec multiple files
 	# VCS
 	vcs => 0,
-	vcs_flags => [split(/\s+/,"+cli -I +define+vcs+1 -q +v2k")],
+	vcs_flags => [split(/\s+/,"+cli -I +define+vcs+1 -q -sverilog")],
 	vcs_flags2 => [],  # Overridden in some sim files
 	# NC
 	nc => 0,
@@ -255,7 +255,8 @@ sub new {
 	# Verilator
 	'v3' => 0,
 	verilator_flags => ["-cc",
-			    "-Mdir $self->{obj_dir}"],
+			    "-Mdir $self->{obj_dir}",
+			    "--debug-check"],
 	verilator_flags2 => [],
 	verilator_make_gcc => 1,
 	verilated_debug => $Opt_Verilated_Debug,

test_regress/t/t_display.v

@@ -52,7 +52,7 @@ module sub;
       begin
 	 $write("[%0t] In %m\n", $time);
 	 begin : subblock
-	    $write("[%0t] In %m\n", $time);
+	    $write("[%0t] In %M\n", $time); // Uppercase %M test
 	 end
       end
    endtask

test_regress/t/t_flag_bboxsys.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 v_flags2 => ["--bbox-sys"],
+	 ) if $Self->{v3};
+
+execute (
+	 check_finished=>1,
+	 ) if $Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_flag_bboxsys.v

@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module a;
+   reg a;
+   initial begin
+      $unknown_sys_task_call_to_be_bbox("blah");
+      a = $unknown_sys_func_call(23);
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

test_regress/t/t_gen_inc.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_gen_inc.v

@@ -0,0 +1,93 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+   integer 	cyc=0;
+
+   genvar g;
+
+   reg [31:0] gen_pre_PLUSPLUS = 32'h0;
+   reg [31:0] gen_pre_MINUSMINUS = 32'h0;
+   reg [31:0] gen_post_PLUSPLUS	= 32'h0;
+   reg [31:0] gen_post_MINUSMINUS = 32'h0;
+   reg [31:0] gen_PLUSEQ = 32'h0;
+   reg [31:0] gen_MINUSEQ = 32'h0;
+   reg [31:0] gen_TIMESEQ = 32'h0;
+   reg [31:0] gen_DIVEQ = 32'h0;
+   reg [31:0] gen_MODEQ = 32'h0;
+   reg [31:0] gen_ANDEQ = 32'h0;
+   reg [31:0] gen_OREQ = 32'h0;
+   reg [31:0] gen_XOREQ	= 32'h0;
+   reg [31:0] gen_SLEFTEQ = 32'h0;
+   reg [31:0] gen_SRIGHTEQ = 32'h0;
+   reg [31:0] gen_SSRIGHTEQ = 32'h0;
+
+   generate
+      for (g=8; g<=16; ++g) always @(posedge clk) gen_pre_PLUSPLUS[g] = 1'b1;
+      for (g=16; g>=8; --g) always @(posedge clk) gen_pre_MINUSMINUS[g] = 1'b1;
+      for (g=8; g<=16; g++) always @(posedge clk) gen_post_PLUSPLUS[g] = 1'b1;
+      for (g=16; g>=8; g--) always @(posedge clk) gen_post_MINUSMINUS[g] = 1'b1;
+      for (g=8; g<=16; g+=2) always @(posedge clk) gen_PLUSEQ[g] = 1'b1;
+      for (g=16; g>=8; g-=2) always @(posedge clk) gen_MINUSEQ[g] = 1'b1;
+`ifndef verilator //UNSUPPORTED
+      for (g=8; g<=16; g*=2) always @(posedge clk) gen_TIMESEQ[g] = 1'b1;
+      for (g=16; g>=8; g/=2) always @(posedge clk) gen_DIVEQ[g] = 1'b1;
+      for (g=15; g>8;  g%=8) always @(posedge clk) gen_MODEQ[g] = 1'b1;
+      for (g=7; g>4;   g&=4) always @(posedge clk) gen_ANDEQ[g] = 1'b1;
+      for (g=1; g<=1;  g|=2) always @(posedge clk) gen_OREQ[g] = 1'b1;
+      for (g=7; g==7;  g^=2) always @(posedge clk) gen_XOREQ[g] = 1'b1;
+      for (g=8; g<=16; g<<=2) always @(posedge clk) gen_SLEFTEQ[g] = 1'b1;
+      for (g=16; g>=8; g>>=2) always @(posedge clk) gen_SRIGHTEQ[g] = 1'b1;
+      for (g=16; g>=8; g>>>=2) always @(posedge clk) gen_SSRIGHTEQ[g] = 1'b1;
+`endif
+   endgenerate
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc == 3) begin
+`ifdef TEST_VERBOSE
+	 $write("gen_pre_PLUSPLUS     %b\n", gen_pre_PLUSPLUS);
+	 $write("gen_pre_MINUSMINUS   %b\n", gen_pre_MINUSMINUS);
+	 $write("gen_post_PLUSPLUS    %b\n", gen_post_PLUSPLUS);
+	 $write("gen_post_MINUSMINUS  %b\n", gen_post_MINUSMINUS);
+	 $write("gen_PLUSEQ           %b\n", gen_PLUSEQ);
+	 $write("gen_MINUSEQ          %b\n", gen_MINUSEQ);
+	 $write("gen_TIMESEQ          %b\n", gen_TIMESEQ);
+	 $write("gen_DIVEQ            %b\n", gen_DIVEQ);
+	 $write("gen_MODEQ            %b\n", gen_MODEQ);
+	 $write("gen_ANDEQ            %b\n", gen_ANDEQ);
+	 $write("gen_OREQ             %b\n", gen_OREQ);
+	 $write("gen_XOREQ            %b\n", gen_XOREQ);
+	 $write("gen_SLEFTEQ          %b\n", gen_SLEFTEQ);
+	 $write("gen_SRIGHTEQ         %b\n", gen_SRIGHTEQ);
+	 $write("gen_SSRIGHTEQ        %b\n", gen_SSRIGHTEQ);
+`endif
+	 if (gen_pre_PLUSPLUS	!== 32'b00000000000000011111111100000000) $stop;
+	 if (gen_pre_MINUSMINUS	!== 32'b00000000000000011111111100000000) $stop;
+	 if (gen_post_PLUSPLUS	!== 32'b00000000000000011111111100000000) $stop;
+	 if (gen_post_MINUSMINUS!== 32'b00000000000000011111111100000000) $stop;
+	 if (gen_PLUSEQ		!== 32'b00000000000000010101010100000000) $stop;
+	 if (gen_MINUSEQ	!== 32'b00000000000000010101010100000000) $stop;
+`ifndef verilator //UNSUPPORTED
+	 if (gen_TIMESEQ	!== 32'b00000000000000010000000100000000) $stop;
+	 if (gen_DIVEQ		!== 32'b00000000000000010000000100000000) $stop;
+	 if (gen_MODEQ		!== 32'b00000000000000001000000000000000) $stop;
+	 if (gen_ANDEQ		!== 32'b00000000000000000000000010000000) $stop;
+	 if (gen_OREQ		!== 32'b00000000000000000000000000000010) $stop;
+	 if (gen_XOREQ		!== 32'b00000000000000000000000010000000) $stop;
+	 if (gen_SLEFTEQ	!== 32'b00000000000000000000000100000000) $stop;
+	 if (gen_SRIGHTEQ	!== 32'b00000000000000010000000000000000) $stop;
+	 if (gen_SSRIGHTEQ	!== 32'b00000000000000010000000000000000) $stop;
+`endif
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+      
+endmodule

test_regress/t/t_preproc.out

@@ -191,4 +191,10 @@ Line_Preproc_Check 131
 (x,y     )
 Line_Preproc_Check 144
 
-`line 146 "t/t_preproc.v" 2
+
+
+ 
+ 
+ 
+x,y)--bee  submacro has comma paren
+`line 152 "t/t_preproc.v" 2

test_regress/t/t_preproc.v

@@ -143,3 +143,9 @@ Line_Preproc_Check `__LINE__
   )
 Line_Preproc_Check `__LINE__
 
+//======================================================================
+// misparsed comma in submacro
+`define sb bee
+`define sa(l) x,y)
+`define sfoo(q,r) q--r
+`sfoo(`sa(el),`sb)  submacro has comma paren

test_regress/t/t_repeat.v

@@ -7,7 +7,6 @@ module t (/*AUTOARG*/);
 
    reg signed [2:0] negcnt;
    integer times;
-   integer repeats;
    initial begin
       times = 0;
       repeat (1) begin
@@ -23,7 +22,6 @@ module t (/*AUTOARG*/);
       end
       if (times != 10) $stop;
       //
-      repeats = 0;
       forever begin
 	 $write("*-* All Finished *-*\n");
 	 $finish;

test_regress/t/t_select_bad_tri.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>$Self->{v3},
+	 expect=>
+q{%Error: t/t_select_bad_tri.v:\d+: Selection index is constantly unknown or tristated: lsb=7'bxxxxxxx width=\?32\?sh47
+%Error: Exiting due to.*},
+	 );
+
+ok(1);
+1;
+

test_regress/t/t_select_bad_tri.v

@@ -0,0 +1,13 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+
+   reg [72:1] in;
+   initial begin
+      if (in[(   (1'h0 / 1'b0)   )+:71] != 71'h0) $stop;
+   end
+
+endmodule

test_regress/t/t_var_bad_sv.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>$Self->{v3},
+	 expect=>
+'%Error: t/t_var_bad_sv.v:\d+: Unexpected "do": "do" is a SystemVerilog keyword misused as an identifier.
+%Error: t/t_var_bad_sv.v:\d+: Modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.
+%Error: t/t_var_bad_sv.v:\d+: Unexpected "do": "do" is a SystemVerilog keyword misused as an identifier.
+.*
+%Error: Exiting due to.*',
+	 );
+
+ok(1);
+1;

test_regress/t/t_var_bad_sv.v

@@ -0,0 +1,9 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+module t;
+   reg do;
+   mod mod (.do(bar));
+endmodule

test_regress/t/t_var_rsvd.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_var_rsvd.v

@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2005 by Wilson Snyder.
+
+// verilator lint_off SYMRSVDWORD
+
+module t (/*AUTOARG*/
+   // Inputs
+   bool
+   );
+
+   input bool;	// BAD
+
+   reg  vector;	// OK, as not public
+   reg  switch /*verilator public*/;	// Bad
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule

test_regress/t/t_var_rsvd_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 fails=>$Self->{v3},
+	 expect=>
+q{%Error-SYMRSVDWORD: t/t_var_rsvd_bad.v:\d+: Symbol matches C\+\+ common word: 'bool'
+%Error-SYMRSVDWORD: t/t_var_rsvd_bad.v:\d+: Symbol matches C\+\+ reserved word: 'switch'
+%Error: Exiting due to.*},
+	 );
+
+ok(1);
+1;

test_regress/t/t_var_rsvd_bad.v

@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2005 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   bool
+   );
+
+   input bool;	// BAD
+
+   reg  vector;	// OK, as not public
+   reg  switch /*verilator public*/;	// Bad
+
+   initial $stop;
+
+endmodule