Version bump

Changes

@@ -3,6 +3,20 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.712 2009/07/14
+
+**   Patching SystemC is no longer required to trace sc_bvs.
+
+***  Support zero-width constants in concatenations.  [Jeff Winston]
+
+***  Add verilator --pins-uint8 option to use sc_in<uint8_t/uint16_t>.
+
+***  Add verilator -V option, to show verbose version.
+
+***  On WIDTH warnings, show variable name causing error.  [Jeff Winston]
+
+**** Add BLKLOOPINIT error code, and describe --unroll-count.  [Jeff Winston]
+
 * Verilator 3.711 2009/06/23
 
 **** Support decimal constants of arbitrary widths. [Mark Marshall]

Makefile.in

@@ -109,8 +109,7 @@ DISTFILES_INC = $(INFOS) .gitignore Artistic COPYING *.in *.ac \
 	MANIFEST.SKIP \
 	bin/* \
 	install-sh configure mkinstalldirs *.texi \
-	include/verilated.[chv]* \
-	include/verilatedos.[chv]* \
+	include/verilated*.[chv]* \
 	include/*.in \
 	include/.*ignore \
 	.*attributes */.*attributes  */*/.*attributes \

bin/verilator

@@ -214,6 +214,7 @@ descriptions in the next sections for more information.
     --output-split <bytes>      Split .cpp files into pieces
     --output-split-cfuncs <statements>   Split .ccp functions
     --pins-bv <bits>            Specify types for top level ports
+    --pins-uint8                Specify types for top level ports
     --prefix <topname>          Name of top level class
     --profile-cfuncs            Name functions for profiling
     --private                   Debugging; see docs
@@ -227,6 +228,7 @@ descriptions in the next sections for more information.
     --trace-depth <levels>      Depth of tracing
     -U<var>                     Undefine preprocessor define
     --underline-zero            Zero signals with leading _'s
+    -V				Verbose version and config
     -v <filename>               Verilog library
     -Werror-<message>           Convert warning to error
     -Wfuture-<message>          Disable unknown message warnings
@@ -513,10 +515,16 @@ Backward compatible alias for "--pins-bv 65".  Note that's a 65, not a 64.
 
 =item --pins-bv I<width>
 
-Specifies SystemC outputs of greater than or equal to I<width> bits wide
-should use sc_bv's instead of uint32/uint64_t's.  The default is "--pins-bv
-65".  Versions before Verilator 3.671 defaulted to "--pins-bv 33".  The
-more sc_bv is used, the worse for performance.
+Specifies SystemC inputs/outputs of greater than or equal to I<width> bits
+wide should use sc_bv's instead of uint32/uint64_t's.  The default is
+"--pins-bv 65".  Versions before Verilator 3.671 defaulted to "--pins-bv
+33".  The more sc_bv is used, the worse for performance.
+
+=item --pins-uint8
+
+Specifies SystemC inputs/outputs that are smaller than the --pins-bv
+setting and 8 bits or less should use uint8_t instead of uint32_t.
+Likewise pins of width 9-16 will use uint16_t instead of uint32_t.
 
 =item --prefix I<topname>
 
@@ -696,6 +704,11 @@ example module I<x> is referenced, look in I<x>.I<ext>.
 
 Undefines the given preprocessor symbol.
 
+=item -V
+
+Shows the verbose version, including configuration information compiled
+into Verilator.  (Similar to perl -V.)
+
 =item -v I<filename>
 
 Read the filename as a Verilog library.  Any modules in the file may be
@@ -1617,17 +1630,9 @@ All specify blocks and timing checks are ignored.
 
 =head2 Array Initialization
 
-When initializing an array, you need to use non-delayed assignments.  This
-is done in the interest of speed; if delayed assignments were used, the
-simulator would have to copy large arrays every cycle.  (In smaller loops,
-loop unrolling allows the delayed assignment to work, though it's a bit
-slower than a non-delayed assignment.)  Here's an example
-
-	always @ (posedge clk)
-            if (~reset_l) begin
-                for (i=0; i<`ARRAY_SIZE; i++) begin
-		    array[i] = 0;	 // Non-delayed for verilator
-                end
+When initializing a large array, you need to use non-delayed assignments.
+Verilator will tell you when this needs to be fixed; see the BLKLOOPINIT
+error for more information.
 
 =head2 Array Out of Bounds
 
@@ -1795,6 +1800,24 @@ inside a public task.
 Ignoring this warning may make Verilator simulations differ from other
 simulators.
 
+=item BLKLOOPINIT
+
+This indicates that the initialization of an array needs to use non-delayed
+assignments.  This is done in the interest of speed; if delayed assignments
+were used, the simulator would have to copy large arrays every cycle.  (In
+smaller loops, loop unrolling allows the delayed assignment to work, though
+it's a bit slower than a non-delayed assignment.)  Here's an example
+
+	always @ (posedge clk)
+            if (~reset_l) begin
+                for (i=0; i<`ARRAY_SIZE; i++) begin
+		    array[i] = 0;	 // Non-delayed for verilator
+                end
+
+This message is only seen on large or complicated loops because Verilator
+generally unrolls small loops.  You may want to try increasing
+--unroll-count which will raise the small loop bar to avoid this error.
+
 =item CASEINCOMPLETE
 
 Warns that inside a case statement there is a stimulus pattern for which

include/verilatedsc.h

@@ -0,0 +1,51 @@
+// -*- C++ -*-
+//*************************************************************************
+//
+// Copyright 2009-2009 by Wilson Snyder. This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License.
+// Version 2.0.
+//
+// Verilator is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+//*************************************************************************
+///
+/// \file
+/// \brief Verilator: Common include for all Verilated SystemC files
+///
+///	This file is included automatically by Verilator at the top of
+///	all SystemC files it generates.
+///
+/// Code available from: http://www.veripool.org/verilator
+///
+//*************************************************************************
+
+
+#ifndef _VERILATEDSC_H_
+#define _VERILATEDSC_H_ 1 ///< Header Guard
+
+#include "verilatedos.h"
+#include "systemc.h"
+
+//=============================================================================
+// VL_SC_BV_DATAP
+// We want to get a pointer to m_data in the sc_bv_base class,
+// but it is protected.  So make an exposing class, then use
+// cast magic to get at it.  Saves patching get_datap in SystemC.
+
+#define VL_SC_BV_DATAP(bv) (VlScBvExposer::sp_datap(bv))
+class VlScBvExposer : public sc_bv_base {
+public:
+    static uint32_t* sp_datap(const sc_bv_base& base) {
+	return static_cast<const VlScBvExposer*>(&base)->sp_datatp(); }
+    uint32_t* sp_datatp() const { return (uint32_t*)(m_data); }
+    // Above reads this protected element in sc_bv_base:
+    //   sc_digit* m_data; // data array
+};
+
+//=========================================================================
+
+#endif // guard

readme.texi

@@ -121,8 +121,7 @@ If you will be using SystemC, download and install System-Perl,
 @url{http://search.cpan.org/search?module=SystemC::Netlist}.  Note
 you'll need to set a @samp{SYSTEMPERL} environment variable to point
 to the downloaded kit.  Optionally also set @samp{SYSTEMPERL_INCLUDE}
-to point to the installed headers.  Also, make sure to do a @code{make
-sc_patch}.
+to point to the installed headers.
 
 @item
 @code{cd} to the Verilator directory containing this README.

src/Makefile.in

@@ -47,7 +47,7 @@ export OBJCACHE_JOBS := -j $(shell objcache --jobs "$(OBJCACHE_HOSTS)")
 export OBJCACHE := @objcache --read --write
 endif
 
-UNDER_GIT = $(wildcard ../.git)
+UNDER_GIT = $(wildcard ../.git/logs/HEAD)
 
 #*********************************************************************
 
@@ -79,7 +79,7 @@ prefiles::
 ifneq ($(UNDER_GIT),)	# If local git tree... Else don't burden users
 prefiles:: config_rev.h
 # This output goes into srcdir, as we need to distribute it as part of the kit.
-config_rev.h:	config_rev.pl ../.git/index
+config_rev.h:	config_rev.pl ../.git/logs/HEAD
 	$(PERL) config_rev.pl . >$@
 endif
 

src/V3Ast.cpp

@@ -176,6 +176,11 @@ string AstNode::prettyName(const string& namein) {
     return pretty;
 }
 
+string AstNode::prettyTypeName() const {
+    if (name()=="") return typeName();
+    return string(typeName())+" '"+prettyName()+"'";
+}
+
 int AstNode::widthPow2() const {
     // I.e.  width 30 returns 32, width 32 returns 32.
     uint32_t width = this->width();

src/V3Ast.h

@@ -640,7 +640,7 @@ protected:
 public:
     // ACCESSORS
     virtual AstType	type() const = 0;
-    const char*	typeName() const { return type().ascii(); }
+    const char*	typeName() const { return type().ascii(); }  // See also prettyTypeName
     AstNode*	nextp() const { return m_nextp; }
     AstNode*	backp() const { return m_backp; }
     AstNode*	op1p() const { return m_op1p; }
@@ -676,6 +676,7 @@ public:
     static string encodeName(const string& namein);	// Encode user name into internal C representation
     static string encodeNumber(vlsint64_t numin);	// Encode number into internal C representation
     string	prettyName() const { return prettyName(name()); }
+    string	prettyTypeName() const;			// "VARREF name" for error messages
     FileLine*	fileline() const { return m_fileline; }
     int		width() const { return m_width; }
     bool	width1() const { return width()==1; }

src/V3AstNodes.cpp

@@ -122,7 +122,13 @@ string AstVar::scType() const {
     } else if (widthMin() == 1) {
 	return "bool";
     } else if (widthMin() <= VL_WORDSIZE) {
-	return "uint32_t";
+	if (widthMin() <= 8 && v3Global.opt.pinsUint8()) {
+	    return "uint8_t";
+	} else if (widthMin() <= 16 && v3Global.opt.pinsUint8()) {
+	    return "uint16_t";
+	} else {
+	    return "uint32_t";
+	}
     } else {
 	return "uint64_t";
     }

src/V3Const.cpp

@@ -1674,7 +1674,7 @@ private:
 	// Default: Just iterate
 	if (m_required) {
 	    nodep->v3error("Expecting expression to be constant, but can't convert a "
-			   <<nodep->typeName()<<" to constant.");
+			   <<nodep->prettyTypeName()<<" to constant.");
 	} else {
 	    // Calculate the width of this operation
 	    if (m_params && !nodep->width()) {

src/V3Delayed.cpp

@@ -335,7 +335,7 @@ private:
 		&& nodep->lhsp()->castSel()->fromp()->castArraySel())) {
 	    AstNode* lhsp = nodep->lhsp()->unlinkFrBack();
 	    AstNode* newlhsp = createDlyArray(nodep, lhsp);
-	    if (m_inLoop) nodep->v3error("Unsupported: Delayed assignment to array inside for loops (non-delayed is ok - see docs)");
+	    if (m_inLoop) nodep->v3warn(BLKLOOPINIT,"Unsupported: Delayed assignment to array inside for loops (non-delayed is ok - see docs)");
 	    if (newlhsp) {
 		nodep->lhsp(newlhsp);
 	    } else {

src/V3EmitC.cpp

@@ -528,9 +528,9 @@ public:
     virtual void visit(AstTraceInc*, AstNUser*) {}	// Handled outside the Visit class
     // Default
     virtual void visit(AstNode* nodep, AstNUser*) {
-	puts((string)"\n???? // "+nodep->typeName()+"\n");
+	puts((string)"\n???? // "+nodep->prettyTypeName()+"\n");
 	nodep->iterateChildren(*this);
-	nodep->v3fatalSrc("Unknown node type reached emitter: "<<nodep->typeName());
+	nodep->v3fatalSrc("Unknown node type reached emitter: "<<nodep->prettyTypeName());
     }
 
 public:
@@ -1885,8 +1885,8 @@ class EmitCTrace : EmitCStmts {
 	if (nodep->valuep()->castVarRef()) {
 	    AstVarRef* varrefp = nodep->valuep()->castVarRef();
 	    AstVar* varp = varrefp->varp();
-	    if (emitTraceIsScBv(nodep)) puts("(uint32_t*)");
 	    puts("(");
+	    if (emitTraceIsScBv(nodep)) puts("VL_SC_BV_DATAP(");
 	    varrefp->iterate(*this);	// Put var name out
 	    if (varp->arraysp()) {
 		if (arrayindex==-2) puts("[i]");
@@ -1894,7 +1894,7 @@ class EmitCTrace : EmitCStmts {
 		else puts("["+cvtToStr(arrayindex)+"]");
 	    }
 	    if (varp->isSc()) puts(".read()");
-	    if (emitTraceIsScBv(nodep)) puts(".get_datap()");
+	    if (emitTraceIsScBv(nodep)) puts(")");
 	    puts(")");
 	} else {
 	    puts("(");

src/V3EmitCBase.h

@@ -68,7 +68,10 @@ public:
     V3OutScFile(const string& filename) : V3OutCFile(filename) {}
     virtual ~V3OutScFile() {};
     virtual void putsHeader() { puts("// Verilated -*- SystemC -*-\n"); }
-    virtual void putsIntTopInclude() { puts("#include \"systemc.h\"\n"); }
+    virtual void putsIntTopInclude() {
+	puts("#include \"systemc.h\"\n");
+	puts("#include \"verilatedsc.h\"\n");
+    }
 };
 
 class V3OutSpFile : public V3OutCFile {
@@ -76,7 +79,10 @@ public:
     V3OutSpFile(const string& filename) : V3OutCFile(filename) {}
     virtual ~V3OutSpFile() {};
     virtual void putsHeader() { puts("// Verilated -*- SystemC -*-\n"); }
-    virtual void putsIntTopInclude() { puts("#include \"systemperl.h\"\n"); }
+    virtual void putsIntTopInclude() {
+	puts("#include \"systemperl.h\"\n");
+	puts("#include \"verilatedsc.h\"\n");
+    }
 };
 
 class V3OutVFile : public V3OutFile {

src/V3EmitV.cpp

@@ -442,9 +442,9 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
     virtual void visit(AstCell*, AstNUser*) {}		// Handled outside the Visit class
     // Default
     virtual void visit(AstNode* nodep, AstNUser*) {
-	puts((string)"\n???? // "+nodep->typeName()+"\n");
+	puts((string)"\n???? // "+nodep->prettyTypeName()+"\n");
 	nodep->iterateChildren(*this);
-	nodep->v3fatalSrc("Unknown node type reached emitter: "<<nodep->typeName());
+	nodep->v3fatalSrc("Unknown node type reached emitter: "<<nodep->prettyTypeName());
     }
 
 public:

src/V3Error.h

@@ -47,6 +47,7 @@ public:
 	// Error codes:
 	MULTITOP,	// Error: Multiple top level modules
 	TASKNSVAR,	// Error: Task I/O not simple
+	BLKLOOPINIT,	// Error: Delayed assignment to array inside for loops
 	// Warning codes:
 	FIRST_WARN,	// Just a code so the program knows where to start warnings
 	//
@@ -88,7 +89,7 @@ public:
 	    // Boolean
 	    " I_COVERAGE", " I_TRACING",
 	    // Errors
-	    "MULTITOP", "TASKNSVAR",
+	    "MULTITOP", "TASKNSVAR", "BLKLOOPINIT",
 	    // Warnings
 	    " FIRST_WARN",
 	    "BLKANDNBLK",

src/V3Hashed.cpp

@@ -65,7 +65,7 @@ private:
 	if (!nodep->user4()) {
 	    if (nodep->backp()->castCFunc()
 		&& !(nodep->castNodeStmt() || nodep->castCFunc())) {
-		nodep->v3fatalSrc("Node "<<nodep->typeName()<<" in statement position but not marked stmt (node under function)");
+		nodep->v3fatalSrc("Node "<<nodep->prettyTypeName()<<" in statement position but not marked stmt (node under function)");
 	    }
 	    V3Hash oldHash = m_lowerHash;
 	    {

src/V3Options.cpp

@@ -624,9 +624,12 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 		shift;
 		V3Options::addLibraryFile(filenameSubstitute(argv[i]));
 	    }
+	    else if ( !strcmp (sw, "-V") ) {
+		showVersion(true);
+		exit(0);
+	    }
 	    else if ( !strcmp (sw, "-version") ) {
-		cout <<version();
-		cout <<endl;
+		showVersion(false);
 		exit(0);
 	    }
 	    // Single switches
@@ -650,6 +653,7 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 	    else if ( onoff   (sw, "-lint-only", flag/*ref*/) )	{ m_lintOnly = flag; }
 	    else if ( !strcmp (sw, "-no-pins64") )		{ m_pinsBv = 33; }
 	    else if ( !strcmp (sw, "-pins64") )			{ m_pinsBv = 65; }
+	    else if ( onoff   (sw, "-pins-uint8", flag/*ref*/) ){ m_pinsUint8 = flag; }
 	    else if ( !strcmp (sw, "-private") )		{ m_public = false; }
 	    else if ( onoff   (sw, "-profile-cfuncs", flag/*ref*/) )	{ m_profileCFuncs = flag; }
 	    else if ( onoff   (sw, "-psl", flag/*ref*/) )		{ m_psl = flag; }
@@ -886,6 +890,41 @@ void V3Options::parseOptsFile(FileLine* fl, const string& filename) {
 
 //======================================================================
 
+void V3Options::showVersion(bool verbose) {
+    cout <<version();
+    cout <<endl;
+    if (!verbose) return;
+
+    cout <<endl;
+    cout << "Copyright 2003-2009 by Wilson Snyder.  Verilator is free software; you can\n";
+    cout << "redistribute it and/or modify the Verilator internals under the terms of\n";
+    cout << "either the GNU Lesser General Public License Version 3 or the Perl Artistic\n";
+    cout << "License Version 2.0.\n";
+
+    cout <<endl;
+    cout << "See http://www.veripool.org/verilator for documentation\n";
+
+    cout <<endl;
+    cout << "Summary of configuration:\n";
+    cout << "  Compiled in defaults if not in environment:\n";
+    cout << "    SYSTEMC            = " << DEFENV_SYSTEMC<<endl;
+    cout << "    SYSTEMC_ARCH       = " << DEFENV_SYSTEMC_ARCH<<endl;
+    cout << "    SYSTEMPERL         = " << DEFENV_SYSTEMPERL<<endl;
+    cout << "    SYSTEMPERL_INCLUDE = " << DEFENV_SYSTEMPERL_INCLUDE<<endl;
+    cout << "    VERILATOR_ROOT     = " << DEFENV_VERILATOR_ROOT<<endl;
+
+    cout <<endl;
+    cout << "Environment:\n";
+    cout << "    PERL               = " << getenvStr("PERL","")<<endl;
+    cout << "    SYSTEMC            = " << getenvStr("SYSTEMC","")<<endl;
+    cout << "    SYSTEMC_ARCH       = " << getenvStr("SYSTEMC_ARCH","")<<endl;
+    cout << "    SYSTEMPERL         = " << getenvStr("SYSTEMPERL","")<<endl;
+    cout << "    SYSTEMPERL_INCLUDE = " << getenvStr("SYSTEMPERL_INCLUDE","")<<endl;
+    cout << "    VERILATOR_ROOT     = " << getenvStr("VERILATOR_ROOT","")<<endl;
+}
+
+//======================================================================
+
 V3Options::V3Options() {
     m_impp = new V3OptionsImp;
 

src/V3Options.h

@@ -105,6 +105,7 @@ class V3Options {
     bool	m_l2Name;	// main switch: --l2name
     bool	m_lintOnly;	// main switch: --lint-only
     bool	m_outFormatOk;	// main switch: --cc, --sc or --sp was specified
+    bool	m_pinsUint8;	// main switch: --pins-uint8
     bool	m_profileCFuncs;// main switch: --profile-cfuncs
     bool	m_psl;		// main switch: --psl
     bool	m_public;	// main switch: --public
@@ -166,8 +167,10 @@ class V3Options {
     void addIncDir(const string& incdir);
     void addLibExt(const string& libext);
     void optimize(int level);
+    void showVersion(bool verbose);
     void coverage(bool flag) { m_coverageLine = m_coverageToggle = m_coverageUser = flag; }
     bool onoff(const char* sw, const char* arg, bool& flag);
+
     static bool wildmatchi(const char* s, const char* p);
     static string getenvStr(const string& envvar, const string& defaultValue);
     static void setenvStr(const string& envvar, const string& value, const string& why);
@@ -212,6 +215,7 @@ class V3Options {
     bool traceDups() const { return m_traceDups; }
     bool outFormatOk() const { return m_outFormatOk; }
     bool keepTempFiles() const { return (V3Error::debugDefault()!=0); }
+    bool pinsUint8() const { return m_pinsUint8; }
     bool profileCFuncs() const { return m_profileCFuncs; }
     bool psl() const { return m_psl; }
     bool allPublic() const { return m_public; }
@@ -290,13 +294,13 @@ class V3Options {
     // METHODS (environment)
     // Most of these may be built into the executable with --enable-defenv,
     // see the README.  If adding new variables, also see src/Makefile_obj.in
+    // Also add to V3Options::showVersion()
     static string getenvPERL() { return getenvStr("PERL","perl"); }
     static string getenvSYSTEMC();
     static string getenvSYSTEMC_ARCH();
     static string getenvSYSTEMPERL();
     static string getenvSYSTEMPERL_INCLUDE();
     static string getenvVERILATOR_ROOT();
-    static string getenvW() { return getenvStr("W",""); }
 
     // METHODS (file utilities using these options)
     string fileExists (const string& filename);

src/V3Table.cpp

@@ -291,7 +291,7 @@ private:
 	}
     }
     virtual void visit(AstNodeCond* nodep, AstNUser*) {
-	// We could use above visit(AstNodeTriop), but it's slower to evaluate
+	// We could use above visit(AstNodeTriop), but it's slower even O(n^2) to evaluate
 	// both sides when we really only need to evaluate one side.
 	if (m_checking) {
 	    if (!optimizable()) return;  // Accelerate
@@ -328,7 +328,7 @@ private:
 	    nodep->rhsp()->iterateAndNext(*this);
 	    AstVarScope* vscp = nodep->lhsp()->castVarRef()->varScopep();
 	    if (nodep->castAssignDly()) {
-		// Don't do setNumber, as value isn't visible to new statements
+		// Don't do setNumber, as value isn't yet visible to following statements
 		setOutNumber(vscp, fetchNumber(nodep->rhsp()));
 	    } else {
 		setNumber(vscp, fetchNumber(nodep->rhsp()));
@@ -353,7 +353,7 @@ private:
 		// In production code, we'll just not optimize.  It should be fixed though.
 		clearOptimizable(nodep, "Unknown node type, perhaps missing visitor in TableSimulateVisitor");
 #ifdef VL_DEBUG
-		UINFO(0,"Unknown node type in TableSimulateVisitor: "<<nodep->typeName()<<endl);
+		UINFO(0,"Unknown node type in TableSimulateVisitor: "<<nodep->prettyTypeName()<<endl);
 #endif
 	    }
 	} else { // simulating

src/V3Width.cpp

@@ -202,6 +202,22 @@ private:
 	    nodep->rhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
 	    nodep->width(nodep->lhsp()->width() + nodep->rhsp()->width(),
 			 nodep->lhsp()->widthMin() + nodep->rhsp()->widthMin());
+	    // Cleanup zero width Verilog2001 {x,{0{foo}}} now,
+	    // otherwise having width(0) will cause later assertions to fire
+	    if (AstReplicate* repp=nodep->lhsp()->castReplicate()) {
+		if (repp->width()==0) {  // Keep rhs
+		    nodep->replaceWith(nodep->rhsp()->unlinkFrBack());
+		    pushDeletep(nodep); nodep=NULL;
+		    return;
+		}
+	    }
+	    if (AstReplicate* repp=nodep->rhsp()->castReplicate()) {
+		if (repp->width()==0) {  // Keep lhs
+		    nodep->replaceWith(nodep->lhsp()->unlinkFrBack());
+		    pushDeletep(nodep); nodep=NULL;
+		    return;
+		}
+	    }
 	}
 	if (vup->c()->final()) {
 	    if (!nodep->widthSized()) {
@@ -218,7 +234,9 @@ private:
 	    AstConst* constp = nodep->rhsp()->castConst();
 	    if (!constp) { nodep->v3error("Replication value isn't a constant."); return; }
 	    uint32_t times = constp->toUInt();
-	    if (times==0) { nodep->v3error("Replication value is 0."); times=1; }
+	    if (times==0 && !nodep->backp()->castConcat()) {  // Concat Visitor will clean it up.
+		nodep->v3error("Replication value of 0 is only legal under a concatenation."); times=1;
+	    }
 	    nodep->width((nodep->lhsp()->width() * times),
 			 (nodep->lhsp()->widthMin() * times));
 	}
@@ -702,7 +720,7 @@ private:
 		    // (Because we need to know if to connect to one or all instants)
 		    nodep->v3error("Port connection "<<nodep->prettyName()<<" as part of a module instance array "
 				   <<" requires "<<pinwidth<<" or "<<pinwidth*numInsts
-				   <<" bits, but connection's "<<nodep->exprp()->typeName()
+				   <<" bits, but connection's "<<nodep->exprp()->prettyTypeName()
 				   <<" generates "<<expwidth<<" bits.");
 		    awidth = expwidth;
 		}
@@ -712,7 +730,7 @@ private:
 		    if (pinwidth != expwidth) {
 			nodep->v3error("Unsupported: Port connection "<<nodep->prettyName()<<" to inout signal "
 				       <<" requires "<<pinwidth
-				       <<" bits, but connection's "<<nodep->exprp()->typeName()
+				       <<" bits, but connection's "<<nodep->exprp()->prettyTypeName()
 				       <<" generates "<<expwidth<<" bits.");
 			// otherwise would need some mess to force both sides to proper size
 		    }
@@ -946,11 +964,11 @@ void WidthVisitor::widthCheck (AstNode* nodep, const char* side,
     }
     if (bad && !ignoreWarn) {
 	if (debug()>4) nodep->backp()->dumpTree(cout,"  back: ");
-	nodep->v3warn(WIDTH,"Operator "<<nodep->typeName()
+	nodep->v3warn(WIDTH,"Operator "<<nodep->prettyTypeName()
 		      <<" expects "<<expWidth
 		      <<(expWidth!=expWidthMin?" or "+cvtToStr(expWidthMin):"")
 		      <<" bits on the "<<side<<", but "<<side<<"'s "
-		      <<underp->typeName()<<" generates "<<underp->width()
+		      <<underp->prettyTypeName()<<" generates "<<underp->width()
 		      <<(underp->width()!=underp->widthMin()
 			 ?" or "+cvtToStr(underp->widthMin()):"")
 		      <<" bits.");
@@ -969,9 +987,9 @@ void WidthVisitor::widthCheckReduce (AstNode* nodep, const char* side,
     if (bad) {
 	if (!ignoreWarn) {
 	    if (debug()>4) nodep->backp()->dumpTree(cout,"  back: ");
-	    nodep->v3warn(WIDTH,"Logical Operator "<<nodep->typeName()
+	    nodep->v3warn(WIDTH,"Logical Operator "<<nodep->prettyTypeName()
 			  <<" expects 1 bit on the "<<side<<", but "<<side<<"'s "
-			  <<underp->typeName()<<" generates "<<underp->width()
+			  <<underp->prettyTypeName()<<" generates "<<underp->width()
 			  <<(underp->width()!=underp->widthMin()
 			     ?" or "+cvtToStr(underp->widthMin()):"")
 			  <<" bits.");
@@ -988,7 +1006,7 @@ void WidthVisitor::widthCheckPin (AstNode* nodep, AstNode* underp, int expWidth,
 		      <<" port connection "<<nodep->prettyName()
 		      <<" expects "<<expWidth
 		      <<" bits but connection's "
-		      <<underp->typeName()<<" generates "<<underp->width()
+		      <<underp->prettyTypeName()<<" generates "<<underp->width()
 		      <<(underp->width()!=underp->widthMin()
 			 ?" or "+cvtToStr(underp->widthMin()):"")
 		      <<" bits.");

src/config_build.h.in

@@ -25,7 +25,7 @@
 //**********************************************************************
 //**** Version and host name
 
-#define DTVERSION	"Verilator 3.711 2009/05/19"
+#define DTVERSION	"Verilator 3.712 2009/07/14"
 
 //**********************************************************************
 //**** Functions

test_regress/t/t_EXAMPLE.v

@@ -87,13 +87,8 @@ module Test (/*AUTOARG*/
    // merge the output values into the result vector.
 
    input clk;
-   input  [31:0] in;
-   output [31:0] out;
-
-   /*AUTOREG*/
-   // Beginning of automatic regs (for this module's undeclared outputs)
-   reg [31:0] 		out;
-   // End of automatics
+   input [31:0]      in;
+   output reg [31:0] out;
 
    always @(posedge clk) begin
       out <= in;

test_regress/t/t_flag_werror_bad1.pl

@@ -13,9 +13,9 @@ compile (
 	 v_flags2 => ["--lint-only"],
 	 fails=>$Self->{v3},
 	 expect=>
-'%Warning-WIDTH: t/t_flag_werror.v:\d+: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS.s CONST generates 6 bits.
+q{%Warning-WIDTH: t/t_flag_werror.v:\d+: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS.s CONST '6'h2e' generates 6 bits.
 %Warning-WIDTH: Use .* and lint_on around source to disable this message.
-%Error: Exiting due to',
+%Error: Exiting due to},
 	 ) if $Self->{v3};
 
 ok(1);

test_regress/t/t_flag_werror_bad2.pl

@@ -14,8 +14,8 @@ compile (
 	 fails=>$Self->{v3},
 	 verilator_flags=> [qw(-sp -Werror-WIDTH)],
 	 expect=>
-'%Error-WIDTH: t/t_flag_werror.v:\d+: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS.s CONST generates 6 bits.
-%Error: Exiting due to',
+q{%Error-WIDTH: t/t_flag_werror.v:\d+: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS.s CONST '6'h2e' generates 6 bits.
+%Error: Exiting due to},
 	 ) if $Self->{v3};
 
 ok(1);

test_regress/t/t_func_bad_width.pl

@@ -11,10 +11,10 @@ compile (
 	 v_flags2 => ["--lint-only"],
 	 fails=>$Self->{v3},
 	 expect=>
-'%Warning-WIDTH: t/t_func_bad_width.v:\d+: Operator FUNCREF expects 40 bits on the Function Argument, but Function Argument.s VARREF generates 39 bits.
+q{%Warning-WIDTH: t/t_func_bad_width.v:\d+: Operator FUNCREF 'MUX' expects 40 bits on the Function Argument, but Function Argument's VARREF 'in' generates 39 bits.
 %Warning-WIDTH: Use [^\n]+
-%Warning-WIDTH: t/t_func_bad_width.v:\d+: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS.s FUNCREF generates 32 bits.
-%Error: Exiting due to',
+%Warning-WIDTH: t/t_func_bad_width.v:\d+: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS.s FUNCREF 'MUX' generates 32 bits.
+%Error: Exiting due to},
 	 );
 
 ok(1);

test_regress/t/t_inst_array_bad.pl

@@ -11,8 +11,8 @@ compile (
 	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
-'%Error: t/t_inst_array_bad.v:\d+: Port connection __pinNumber2 as part of a module instance array  requires 1 or 8 bits, but connection\'s VARREF generates 9 bits.
-%Error: Exiting due to.*',
+q{%Error: t/t_inst_array_bad.v:\d+: Port connection __pinNumber2 as part of a module instance array  requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits.
+%Error: Exiting due to.*},
 	 );
 
 ok(1);

test_regress/t/t_inst_overwide_bad.pl

@@ -16,12 +16,12 @@ compile (
 	 verilator_make_gcc=>0,
 	 fails=>$Self->{v3},
 	 expect=>
-'%Warning-WIDTH: t/t_inst_overwide.v:\d+: Output port connection outy_w92 expects 92 bits but connection\'s VARREF generates 30 bits.
+q{%Warning-WIDTH: t/t_inst_overwide.v:\d+: Output port connection outy_w92 expects 92 bits but connection's VARREF 'outc_w30' generates 30 bits.
 %Warning-WIDTH: Use .* to disable this message.
-%Warning-WIDTH: t/t_inst_overwide.v:\d+: Output port connection outz_w22 expects 22 bits but connection\'s VARREF generates 73 bits.
-%Warning-WIDTH: t/t_inst_overwide.v:\d+: Input port connection inw_w31 expects 31 bits but connection\'s VARREF generates 1 bits.
-%Warning-WIDTH: t/t_inst_overwide.v:\d+: Input port connection inx_w11 expects 11 bits but connection\'s VARREF generates 61 bits.
-%Error: Exiting due to.*',
+%Warning-WIDTH: t/t_inst_overwide.v:\d+: Output port connection outz_w22 expects 22 bits but connection's VARREF 'outd_w73' generates 73 bits.
+%Warning-WIDTH: t/t_inst_overwide.v:\d+: Input port connection inw_w31 expects 31 bits but connection's VARREF 'ina_w1' generates 1 bits.
+%Warning-WIDTH: t/t_inst_overwide.v:\d+: Input port connection inx_w11 expects 11 bits but connection's VARREF 'inb_w61' generates 61 bits.
+%Error: Exiting due to.*},
 	 );
 
 ok(1);

test_regress/t/t_lint_restore_bad.pl

@@ -11,9 +11,9 @@ compile (
 	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
-'.*%Warning-WIDTH: t/t_lint_restore_bad.v:\d+: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST generates 64 bits.
+q{.*%Warning-WIDTH: t/t_lint_restore_bad.v:\d+: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits.
 %Warning-WIDTH: Use .*
-%Error: Exiting due to.*',
+%Error: Exiting due to.*},
 	 ) if $Self->{v3};
 
 ok(1);

test_regress/t/t_lint_width_bad.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>1,
+	 expect=>
+q{.*%Warning-WIDTH: t/t_lint_width_bad.v:\d+: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits.
+%Warning-WIDTH: Use .*
+%Error: Exiting due to.*},
+	 ) if $Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_lint_width_bad.v

@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+module t ();
+
+   // This shows the uglyness in width warnings across param modules
+   // TODO: Would be nice to also show relevant parameter settings
+   p #(.WIDTH(4)) p4 (.in(4'd0));
+   p #(.WIDTH(5)) p5 (.in(5'd0));
+
+endmodule
+
+module p
+  #(parameter WIDTH=64)
+   (input [WIDTH-1:0] in);
+   wire [4:0] out = in;
+endmodule

test_regress/t/t_math_concat0.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_math_concat0.v

@@ -0,0 +1,87 @@
+// DESCRIPTION: Verilator: Verilog Test module
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [15:0]  in = crc[15:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [15:0]		outa;			// From test of Test.v
+   wire [15:0]		outb;			// From test of Test.v
+   wire [15:0]		outc;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .outa			(outa[15:0]),
+	      .outb			(outb[15:0]),
+	      .outc			(outc[15:0]),
+	      // Inputs
+	      .clk			(clk),
+	      .in			(in[15:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {16'h0, outa, outb, outc};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+	 sum <= 64'h0;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h09be74b1b0f8c35d
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   outa, outb, outc,
+   // Inputs
+   clk, in
+   );
+
+   input clk;
+   input [15:0]      in;
+   output reg [15:0] outa;
+   output reg [15:0] outb;
+   output reg [15:0] outc;
+
+   parameter WIDTH = 0;
+   always @(posedge clk) begin
+      outa <= {in};
+      outb <= {{WIDTH{1'b0}}, in};
+      outc <= {in, {WIDTH{1'b0}}};
+   end
+endmodule

test_regress/t/t_var_pins_scui.pl

@@ -0,0 +1,34 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_var_pinsizes.v");
+
+compile (
+	 v_flags2 => ["--trace -sp -pins-uint8 --exe $Self->{t_dir}/t_var_pinsizes.cpp"],
+	 make_main => 0,
+	 ) if $Self->{v3};
+
+if ($Self->{v3}) {
+    file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.sp", qr/sc_in<bool> \s+ i1;/x);
+    file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.sp", qr/sc_in<uint8_t> \s+ i8;/x);
+    file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.sp", qr/sc_in<uint16_t> \s+ i16;/x);
+    file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.sp", qr/sc_in<uint32_t> \s+ i32;/x);
+    file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.sp", qr/sc_in<uint64_t> \s+ i64;/x);
+    file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.sp", qr/sc_in<sc_bv<65>\s> \s+ i65;/x);
+
+    file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.sp", qr/sc_out<bool> \s+ o1;/x);
+    file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.sp", qr/sc_out<uint8_t> \s+ o8;/x);
+    file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.sp", qr/sc_out<uint16_t> \s+ o16;/x);
+    file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.sp", qr/sc_out<uint32_t> \s+ o32;/x);
+    file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.sp", qr/sc_out<uint64_t> \s+ o64;/x);
+    file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.sp", qr/sc_out<sc_bv<65>\s> \s+ o65;/x);
+}
+
+ok(1);
+1;

test_regress/t/t_var_pinsizes.cpp

@@ -8,6 +8,8 @@
 # include "Vt_var_pins_sc32.h"
 #elif defined(T_VAR_PINS_SC64)
 # include "Vt_var_pins_sc64.h"
+#elif defined(T_VAR_PINS_SCUI)
+# include "Vt_var_pins_scui.h"
 #else
 # error "Unknown test"
 #endif