Version bump

git-svn-id: file://localhost/svn/verilator/trunk/verilator@1053 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -3,6 +3,18 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.663 2008/05/07
+
+**** Add DESTDIR to Makefiles to assist RPM construction. [Gunter Dannoritzer]
+
+**** Fix compiler warnings under GCC 4.2.1.
+
+**** Fix preprocessor `else after series of `elsif.  [Mark Nodine]
+
+**** Fix parametrized defines calling define with comma.  [Joshua Wise]
+
+**** Fix comma separated list of primitives.  [by Bryan Brady]
+
 * Verilator 3.662 2008/04/25
 
 ***  Add Verilog 2005 $clog2() function.

Makefile.in

@@ -61,6 +61,9 @@ MAKEINFO = makeinfo
 TEXI2DVI = texi2dvi
 PERL = @PERL@
 
+# Destination prefix for RPMs
+DESTDIR = 
+
 #### Don't edit: You're much better using configure switches to set these
 prefix = @prefix@
 exec_prefix = @exec_prefix@
@@ -81,6 +84,9 @@ infodir = @infodir@
 # Generally ${prefix}/share/verilator
 pkgdatadir = @pkgdatadir@
 
+# Directory in which to install data across multiple architectures
+datarootdir = @datarootdir@
+
 #### End of system configuration section. ####
 ######################################################################
 
@@ -210,26 +216,26 @@ README: readme.texi
 # See uninstall also
 VL_INST_BIN_FILES = verilator verilator_bin verilator_bin_dbg
 installbin:
-	$(SHELL) ${srcdir}/mkinstalldirs $(bindir)
-	( cd bin ; $(INSTALL_PROGRAM) verilator $(bindir)/verilator )
-	( $(INSTALL_PROGRAM) verilator_bin $(bindir)/verilator_bin )
-	( $(INSTALL_PROGRAM) verilator_bin_dbg $(bindir)/verilator_bin_dbg )
+	$(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(bindir)
+	( cd bin ; $(INSTALL_PROGRAM) verilator $(DESTDIR)$(bindir)/verilator )
+	( $(INSTALL_PROGRAM) verilator_bin $(DESTDIR)$(bindir)/verilator_bin )
+	( $(INSTALL_PROGRAM) verilator_bin_dbg $(DESTDIR)$(bindir)/verilator_bin_dbg )
 
 VL_INST_MAN_FILES = verilator.1
 installman:
-	$(SHELL) ${srcdir}/mkinstalldirs $(mandir)
+	$(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(mandir)/man1
 	for p in $(VL_INST_MAN_FILES) ; do \
-	  $(INSTALL_PROGRAM) $$p $(mandir)/man1/$$p; \
+	  $(INSTALL_PROGRAM) $$p $(DESTDIR)$(mandir)/man1/$$p; \
 	done
 
 installdata:
-	$(SHELL) ${srcdir}/mkinstalldirs $(pkgdatadir)/examples
-	cp -r include $(pkgdatadir)
-	cp -r src     $(pkgdatadir)
-	cp -r test_c  $(pkgdatadir)/examples
-	cp -r test_sc $(pkgdatadir)/examples
-	cp -r test_sp $(pkgdatadir)/examples
-	cp -r test_v  $(pkgdatadir)/examples
+	$(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(pkgdatadir)/examples
+	cp -r include $(DESTDIR)$(pkgdatadir)
+	cp -r src     $(DESTDIR)$(pkgdatadir)
+	cp -r test_c  $(DESTDIR)$(pkgdatadir)/examples
+	cp -r test_sc $(DESTDIR)$(pkgdatadir)/examples
+	cp -r test_sp $(DESTDIR)$(pkgdatadir)/examples
+	cp -r test_v  $(DESTDIR)$(pkgdatadir)/examples
 
 VL_INST_DATA_FILES = verilator.1
 install: all_nomsg installbin installman installdata install-msg
@@ -273,9 +279,9 @@ install-msg:
 	@echo
 
 uninstall:
-	-cd $(mandir)/man1 && rm -f $(VL_INST_MAN_FILES)
-	-cd $(bindir) && rm -f $(VL_INST_BIN_FILES)
-	-rm -f $(pkgdatadir)
+	-cd $(DESTDIR)$(mandir)/man1 && rm -f $(VL_INST_MAN_FILES)
+	-cd $(DESTDIR)$(bindir) && rm -f $(VL_INST_BIN_FILES)
+	-rm -f $(DESTDIR)$(pkgdatadir)
 
 # autoheader might not change config_build.h.in, so touch a stamp file.
 IN_WILD := ${srcdir}/*.in ${srcdir}/*/*.in ${srcdir}/*/*/*.in \

configure.ac

@@ -12,7 +12,7 @@ dnl Special Substitutions
 AC_ARG_ENABLE(defenv,
    [AS_HELP_STRING([--disable-defenv], [disable hardcoded default environment variables])],
    CFG_WITH_DEFENV=$enableval,
-   CFG_WITH_DEFENV=1)
+   CFG_WITH_DEFENV=yes)
 AC_SUBST(CFG_WITH_DEFENV)
 
 dnl Checks for programs.

src/Makefile_obj.in

@@ -34,6 +34,9 @@ CFG_WITH_DEFENV = @CFG_WITH_DEFENV@
 
 prefix = @prefix@
 
+# Directory in which to install data across multiple architectures
+datarootdir = @datarootdir@
+
 # Directory in which to install package specific files
 # Generally ${prefix}/share/verilator
 pkgdatadir = @pkgdatadir@
@@ -242,14 +245,19 @@ V3PreProc.o:	V3PreProc.cpp V3PreLex.yy.cpp
 #### Generated files
 
 # Target rule called before parallel build to make generated files
-serial:: V3Ast__gen_classes.h
+serial:: V3Ast__gen_classes.h y.tab.c
 
 V3Ast__gen_classes.h : $(ASTGEN) V3Ast.h V3AstNodes.h
 	$(PERL) $(ASTGEN) -I$(srcdir)  --classes
 
-y.tab.c y.tab.h:	verilog.y $(HEADERS)
+y.tab.h: y.tab.c
+
+# Have only one output file in this rule to prevent parallel make issues
+y.tab.c: verilog.y $(HEADERS)
 	@echo "If you get errors from verilog.y below, try upgrading bison to version 1.875 or newer."
 	${YACC} ${YFLAGS} $<
+	mv y.tab.c y_pregen.tab.c && $(PERL) $(srcdir)/bisonfix < y_pregen.tab.c > y.tab.c
+	mv y.tab.h y_pregen.tab.h && $(PERL) $(srcdir)/bisonfix < y_pregen.tab.h > y.tab.h
 
 V3Lexer_pregen.yy.cpp:	verilog.l y.tab.h $(HEADERS)
 	${LEX} ${LFLAGS} -o$@ $<

src/V3PreLex.l

@@ -36,6 +36,7 @@ static void linenoInc()  {V3PreLex::s_currentLexp->incLineno();}
 static bool optPsl() { return V3PreProc::optPsl(); }
 static bool pedantic() { return V3PreLex::s_currentLexp->m_pedantic; }
 static void yyerror(char* msg) { V3PreLex::s_currentLexp->m_curFilelinep->v3error(msg); }
+static void yyerrorf(const char* msg) { V3PreLex::s_currentLexp->m_curFilelinep->v3error(msg); }
 static void appendDefValue(char* t,int l) { V3PreLex::s_currentLexp->appendDefValue(t,l); }
 static int  pslParenLevel()    { return V3PreLex::s_currentLexp->m_pslParenLevel; }
 static void pslParenLevelInc() { V3PreLex::s_currentLexp->m_pslParenLevel++; }
@@ -100,8 +101,8 @@ psl		[p]sl
 
 	/* Pass-through strings */
 <INITIAL,PSLMULM,PSLONEM>{quote}	{ yy_push_state(STRMODE); yymore(); }
-<STRMODE><<EOF>>	{ linenoInc(); yyerror("EOF in unterminated string"); yyleng=0; yyterminate(); }
-<STRMODE>{crnl}		{ linenoInc(); yyerror("Unterminated string"); BEGIN(INITIAL); }
+<STRMODE><<EOF>>	{ linenoInc(); yyerrorf("EOF in unterminated string"); yyleng=0; yyterminate(); }
+<STRMODE>{crnl}		{ linenoInc(); yyerrorf("Unterminated string"); BEGIN(INITIAL); }
 <STRMODE>[^\"\\]	{ yymore(); }
 <STRMODE>{backslash}.	{ yymore(); }
 <STRMODE>{quote} 	{ yy_pop_state();
@@ -110,14 +111,14 @@ psl		[p]sl
 
 	/* Protected blocks */
 <INITIAL>"`protected"	{ yy_push_state(PRTMODE); yymore(); }
-<PRTMODE><<EOF>>	{ linenoInc(); yyerror("EOF in `protected"); yyleng=0; yyterminate(); }
+<PRTMODE><<EOF>>	{ linenoInc(); yyerrorf("EOF in `protected"); yyleng=0; yyterminate(); }
 <PRTMODE>{crnl}		{ linenoInc(); yymore(); }
 <PRTMODE>.	 	{ yymore(); }
 <PRTMODE>"`endprotected" { yy_pop_state(); return (VP_TEXT); }
 
 	/* Pass-through include <> filenames */
-<INCMODE><<EOF>>	{ linenoInc(); yyerror("EOF in unterminated include filename"); yyleng=0; yyterminate(); }
-<INCMODE>{crnl}		{ linenoInc(); yyerror("Unterminated include filename"); BEGIN(INITIAL); }
+<INCMODE><<EOF>>	{ linenoInc(); yyerrorf("EOF in unterminated include filename"); yyleng=0; yyterminate(); }
+<INCMODE>{crnl}		{ linenoInc(); yyerrorf("Unterminated include filename"); BEGIN(INITIAL); }
 <INCMODE>[^\>\\]	{ yymore(); }
 <INCMODE>{backslash}.	{ yymore(); }
 <INCMODE>[\>]	 	{ yy_pop_state(); return (VP_STRING); }
@@ -126,9 +127,9 @@ psl		[p]sl
 <DEFMODE>"/*"		{ yy_push_state(CMTMODE); yymore(); }
 <DEFMODE>"//"[^\n\r]*	{ return (VP_COMMENT);}
 <DEFMODE>{drop}		{ }
-<DEFMODE><<EOF>>	{ linenoInc(); yy_pop_state(); yytext="\n"; yyleng=1; return (VP_DEFVALUE); } /* Technically illegal, but people complained */
-<DEFMODE>{crnl}		{ linenoInc(); yy_pop_state(); yytext="\n"; yyleng=1; return (VP_DEFVALUE); }
-<DEFMODE>[\\]{crnl}	{ linenoInc(); appendDefValue("\n",1); } /* Include return so can maintain output line count */
+<DEFMODE><<EOF>>	{ linenoInc(); yy_pop_state(); yytext=(char*)"\n"; yyleng=1; return (VP_DEFVALUE); } /* Technically illegal, but people complained */
+<DEFMODE>{crnl}		{ linenoInc(); yy_pop_state(); yytext=(char*)"\n"; yyleng=1; return (VP_DEFVALUE); }
+<DEFMODE>[\\]{crnl}	{ linenoInc(); appendDefValue((char*)"\n",1); } /* Include return so can maintain output line count */
 <DEFMODE>[^\/\*\n\r\\]+	|
 <DEFMODE>[\\][^\n\r]	|
 <DEFMODE>.		{ appendDefValue(yytext,yyleng); }
@@ -137,8 +138,8 @@ psl		[p]sl
 <ARGMODE>"/*"		{ yy_push_state(CMTMODE); yymore(); }
 <ARGMODE>"//"[^\n\r]*	{ return (VP_COMMENT);}
 <ARGMODE>{drop}		{ }
-<ARGMODE><<EOF>>	{ yyerror("EOF in define argument list\n"); yyleng = 0; yyterminate(); }
-<ARGMODE>{crnl}		{ linenoInc(); yytext="\n"; yyleng=1; return(VP_WHITE); }
+<ARGMODE><<EOF>>	{ yyerrorf("EOF in define argument list\n"); yyleng = 0; yyterminate(); }
+<ARGMODE>{crnl}		{ linenoInc(); yytext=(char*)"\n"; yyleng=1; return(VP_WHITE); }
 <ARGMODE>{quote}	{ yy_push_state(STRMODE); yymore(); }
 <ARGMODE>[(]		{ V3PreLex::s_currentLexp->m_parenLevel++;
 			  // Note paren level 0 means before "(" of starting args
@@ -167,7 +168,7 @@ psl		[p]sl
 	/* One line comments. */
 <INITIAL>"//"{ws}*{psl} { if (optPsl())        { pslMoreNeeded(true); yy_push_state(PSLONEM); return(VP_PSL); }
 			  else { yy_push_state(CMTONEM); yymore(); } }
-<INITIAL>"//"{ws}*{crnl} { linenoInc(); yytext="\n"; yyleng=1; return (VP_WHITE); }
+<INITIAL>"//"{ws}*{crnl} { linenoInc(); yytext=(char*)"\n"; yyleng=1; return (VP_WHITE); }
 <INITIAL>"//" 		{ if (pslMoreNeeded()) { pslMoreNeeded(true); yy_push_state(PSLONEM); return(VP_PSL); }
 			  else { yy_push_state(CMTONEM); yymore(); } }
 <CMTONEM>[^\n\r]* 	{ yy_pop_state(); return (VP_COMMENT); }
@@ -176,13 +177,13 @@ psl		[p]sl
 <PSLONEM>[{(]		{ pslParenLevelInc(); return (VP_TEXT); }
 <PSLONEM>[})]		{ pslParenLevelDec(); return (VP_TEXT); }
 <PSLONEM>[;]		{ if (!pslParenLevel()) {BEGIN PSLONEE; pslMoreNeeded(false);} return (VP_TEXT); }
-<PSLONEM><<EOF>>	{ yyerror("EOF in '/* ... */' psl comment\n"); yyleng=0; yyterminate(); }
-<PSLONEM>{crnl}		{ linenoInc(); yy_pop_state(); yytext="\n"; yyleng=1; return(VP_WHITE); }
+<PSLONEM><<EOF>>	{ yyerrorf("EOF in '/* ... */' psl comment\n"); yyleng=0; yyterminate(); }
+<PSLONEM>{crnl}		{ linenoInc(); yy_pop_state(); yytext=(char*)"\n"; yyleng=1; return(VP_WHITE); }
 
 	/* Completed psl oneline comments */
-<PSLONEE>{crnl}		{ linenoInc(); yy_pop_state(); yytext="\n"; yyleng=1; return(VP_WHITE); }
+<PSLONEE>{crnl}		{ linenoInc(); yy_pop_state(); yytext=(char*)"\n"; yyleng=1; return(VP_WHITE); }
 <PSLONEE>{ws}+		{ yymore(); }
-<PSLONEE>.		{ yyerror("Unexpected text following psl assertion\n"); }
+<PSLONEE>.		{ yyerrorf("Unexpected text following psl assertion\n"); }
 
 	/* C-style comments. */
 	/* We distinguish between the start of a comment, and later, so we may find a "psl" prefix */
@@ -191,7 +192,7 @@ psl		[p]sl
 <CMTBEGM>{ws}+		{ yymore(); }
 <CMTBEGM,CMTMODE>"*/"		{ yy_pop_state(); return(VP_COMMENT); }
 <CMTBEGM,CMTMODE>{crnl}		{ linenoInc(); yymore(); }
-<CMTBEGM,CMTMODE><<EOF>>	{ yyerror("EOF in '/* ... */' block comment\n"); yyleng=0; yyterminate(); }
+<CMTBEGM,CMTMODE><<EOF>>	{ yyerrorf("EOF in '/* ... */' block comment\n"); yyleng=0; yyterminate(); }
 <CMTBEGM>.			{ BEGIN CMTMODE; yymore(); }	/* Non 'psl' beginning in comment */
 <CMTMODE>.			{ yymore(); }
 
@@ -199,13 +200,13 @@ psl		[p]sl
 <PSLMUL1>.|{crnl}	{ yyless(0); BEGIN PSLMULM; return(VP_PSL); }
 <PSLMULM>"*/"		{ yy_pop_state(); return(VP_COMMENT); }
 <PSLMULM>"//"[^\n\r]*	{ return (VP_COMMENT); }	/* Comments inside block comments get literal inclusion (later removal) */
-<PSLMULM><<EOF>>	{ yyerror("EOF in '/* ... */' psl comment\n"); yyleng=0; yyterminate(); }
+<PSLMULM><<EOF>>	{ yyerrorf("EOF in '/* ... */' psl comment\n"); yyleng=0; yyterminate(); }
 
 	/* Define calls */
 <INITIAL,PSLMULM,PSLONEM>"`"{symb}	{ return (VP_DEFREF); }
 
 	/* Generics */
-<INITIAL,PSLMULM>{crnl}		{ linenoInc(); yytext="\n"; yyleng=1; return(VP_WHITE); }
+<INITIAL,PSLMULM>{crnl}		{ linenoInc(); yytext=(char*)"\n"; yyleng=1; return(VP_WHITE); }
 <INITIAL,PSLMULM,PSLONEM>{symb}	{ return (VP_SYMBOL); }
 <INITIAL,PSLMULM,PSLONEM>{wsn}+	{ return (VP_WHITE); }
 <INITIAL,PSLMULM,PSLONEM>{drop}	{ }

src/V3PreProc.cpp

@@ -83,6 +83,21 @@ public:
     ~V3DefineRef() {}
 };
 
+//*************************************************************************
+/// Data for parsing on/off
+
+class VPreIfEntry {
+    // One for each pending ifdef/ifndef
+    bool	m_on;		// Current parse for this ifdef level is "on"
+    bool	m_everOn;	// Some if term in elsif tree has been on
+public:
+    bool on() const { return m_on; }
+    bool everOn() const { return m_everOn; }
+    VPreIfEntry(bool on, bool everOn)
+	: m_on(on), m_everOn(everOn || on) {}  // Note everOn includes new state
+    ~VPreIfEntry() {}
+};
+
 //*************************************************************************
 // Data for a preprocessor instantiation.
 
@@ -111,7 +126,7 @@ struct V3PreProcImp : public V3PreProc {
 
     // For defines
     stack<V3DefineRef> m_defRefs; // Pending definine substitution
-    stack<bool> m_ifdefStack;	// Stack of true/false emitting evaluations
+    stack<VPreIfEntry> m_ifdefStack;	///< Stack of true/false emitting evaluations
     unsigned	m_defDepth;	// How many `defines deep
 
     // Defines list
@@ -655,7 +670,7 @@ int V3PreProcImp::getToken() {
 		    bool enable = defExists(m_lastSym);
 		    UINFO(4,"Ifdef "<<m_lastSym<<(enable?" ON":" OFF")<<endl);
 		    if (m_stateFor==VP_IFNDEF) enable = !enable;
-		    m_ifdefStack.push(enable);
+		    m_ifdefStack.push(VPreIfEntry(enable,false));
 		    if (!enable) parsingOff();
 		}
 		else if (m_stateFor==VP_ELSIF) {
@@ -663,12 +678,12 @@ int V3PreProcImp::getToken() {
 			fileline()->v3error("`elsif with no matching `if\n");
 		    } else {
 			// Handle `else portion
-			bool lastEnable = m_ifdefStack.top(); m_ifdefStack.pop();
-			if (!lastEnable) parsingOn();
+			VPreIfEntry lastIf = m_ifdefStack.top(); m_ifdefStack.pop();
+			if (!lastIf.on()) parsingOn();
 			// Handle `if portion
-			bool enable = !lastEnable && defExists(m_lastSym);
+			bool enable = !lastIf.everOn() && defExists(m_lastSym);
 			UINFO(4,"Elsif "<<m_lastSym<<(enable?" ON":" OFF")<<endl);
-			m_ifdefStack.push(enable);
+			m_ifdefStack.push(VPreIfEntry(enable, lastIf.everOn()));
 			if (!enable) parsingOff();
 		    }
 		}
@@ -856,21 +871,23 @@ int V3PreProcImp::getToken() {
 	    if (m_ifdefStack.empty()) {
 		fileline()->v3error("`else with no matching `if\n");
 	    } else {
-		bool lastEnable = m_ifdefStack.top(); m_ifdefStack.pop();
-		bool enable = !lastEnable;
+		VPreIfEntry lastIf = m_ifdefStack.top(); m_ifdefStack.pop();
+		bool enable = !lastIf.everOn();
 		UINFO(4,"Else "<<(enable?" ON":" OFF")<<endl);
-		m_ifdefStack.push(enable);
-		if (!lastEnable) parsingOn();
+		m_ifdefStack.push(VPreIfEntry(enable, lastIf.everOn()));
+		if (!lastIf.on()) parsingOn();
 		if (!enable) parsingOff();
 	    }
 	    goto next_tok;
 	case VP_ENDIF:
+	    UINFO(4,"Endif "<<endl);
 	    if (m_ifdefStack.empty()) {
 		fileline()->v3error("`endif with no matching `if\n");
 	    } else {
-		bool lastEnable = m_ifdefStack.top(); m_ifdefStack.pop();
-		UINFO(4,"Endif "<<endl);
-		if (!lastEnable) parsingOn();
+		VPreIfEntry lastIf = m_ifdefStack.top(); m_ifdefStack.pop();
+		if (!lastIf.on()) parsingOn();
+		// parsingOn() really only enables parsing if
+		// all ifdef's above this want it on
 	    }
 	    goto next_tok;
 
@@ -894,7 +911,16 @@ int V3PreProcImp::getToken() {
 			string out = defValue(name);
 			UINFO(4,"Defref `"<<name<<" => '"<<out<<"'"<<endl);
 			// Similar code in parenthesized define (Search for END_OF_DEFARG)
-			m_lexp->unputString(out.c_str());
+			if (m_defRefs.empty()) {
+			    // Just output the substitution
+			    m_lexp->unputString(out.c_str());
+			} else {
+			    // Inside another define.  Can't subst now, or
+			    // `define a x,y
+			    // foo(`a,`b)  would break because a contains comma
+			    V3DefineRef* refp = &(m_defRefs.top());
+			    refp->nextarg(refp->nextarg()+m_lexp->m_defValue+out); m_lexp->m_defValue="";
+			}
 			goto next_tok;
 		    }
 		    else {  // Found, with parameters

src/V3Read.cpp

@@ -61,7 +61,7 @@ public:
     ~V3Lexer() {}
     // METHODS
     void stateExitPsl() {
-	if (YY_START != PSL) yyerror("Internal error: Exiting PSL state when not in PSL state");
+	if (YY_START != PSL) yyerrorf("Internal error: Exiting PSL state when not in PSL state");
 	yy_pop_state();
     }
     void statePushVlg() {

src/bisonfix

@@ -0,0 +1,28 @@
+#!/usr/bin/perl -w
+#$Id$
+######################################################################
+#
+# Copyright 2008-2008 by Wilson Snyder.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of either the GNU General Public License or the
+# Perl Artistic License.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the Perl Artistic License
+# along with this module; see the file COPYING.  If not, see
+# www.cpan.org
+#                                                                           
+######################################################################
+
+# DESCRIPTION: Edits bison output to get around various issues.
+
+foreach my $line (<STDIN>) {
+    # Fix bison 2.3 and GCC 4.2.1
+    $line =~ s!\(YY_\("!(YY_((char*)"!g;
+    print "$line";
+}

src/config_build.h.in

@@ -24,7 +24,7 @@
 //**********************************************************************
 //**** Version and host name
 
-#define DTVERSION	"Verilator 3.662 2008/04/25"
+#define DTVERSION	"Verilator 3.663 2008/05/07"
 
 //**********************************************************************
 //**** Functions

src/verilog.l

@@ -63,7 +63,7 @@ void V3Read::verilatorCmtLintSave() {
 }
 void V3Read::verilatorCmtLintRestore() {
     if (s_readp->m_lintState.empty()) {
-	yyerror("/*verilator lint_restore*/ without matching save.");
+	yyerrorf("/*verilator lint_restore*/ without matching save.");
 	return;
     }
     V3Read::fileline()->warnStateFrom(s_readp->m_lintState.back());
@@ -687,7 +687,7 @@ escid	\\[^ \t\f\r\n]+
 
   /************************************************************************/
   /* STRINGS */
-<STRING>\n 		{ yyerror("Unterminated string\n"); }
+<STRING>\n 		{ yyerrorf("Unterminated string\n"); }
 <STRING>\r		;
 <STRING>[^\"\\]* 	{ yymore(); }
 <STRING>\\.	 	{ yymore(); }
@@ -700,7 +700,7 @@ escid	\\[^ \t\f\r\n]+
 <ATTRMODE>\n		{ yymore(); NEXTLINE(); }
 <ATTRMODE>"*)"		{ yy_pop_state(); } 
 <ATTRMODE>. 		{ yymore(); }
-<ATTRMODE><<EOF>>	{ yyerror("EOF in (*");
+<ATTRMODE><<EOF>>	{ yyerrorf("EOF in (*");
 			  yyleng = 0; yy_pop_state(); }
 
   /************************************************************************/

src/verilog.y

@@ -35,7 +35,7 @@
 
 // Pick up new lexer
 #define yylex V3Read::yylex
-#define PSLUNSUP(what) NULL; yyerror("Unsupported: PSL language feature not implemented");
+#define PSLUNSUP(what) NULL; yyerrorf("Unsupported: PSL language feature not implemented");
 
 extern void yyerror(char* errmsg);
 extern void yyerrorf(const char* format, ...);
@@ -1137,28 +1137,28 @@ gateDecl: 	yBUF  delayE gateBufList ';'		{ $$ = $3; }
 	;
 
 gateBufList:	gateBuf 				{ $$ = $1; }
-	|	gateBuf ',' gateBuf			{ $$ = $1->addNext($3); }
+	|	gateBufList ',' gateBuf			{ $$ = $1->addNext($3); }
 	;
 gateNotList:	gateNot 				{ $$ = $1; }
-	|	gateNot ',' gateNot			{ $$ = $1->addNext($3); }
+	|	gateNotList ',' gateNot			{ $$ = $1->addNext($3); }
 	;
 gateAndList:	gateAnd 				{ $$ = $1; }
-	|	gateAnd ',' gateAnd			{ $$ = $1->addNext($3); }
+	|	gateAndList ',' gateAnd			{ $$ = $1->addNext($3); }
 	;
 gateNandList:	gateNand 				{ $$ = $1; }
-	|	gateNand ',' gateNand			{ $$ = $1->addNext($3); }
+	|	gateNandList ',' gateNand		{ $$ = $1->addNext($3); }
 	;
 gateOrList:	gateOr 					{ $$ = $1; }
-	|	gateOr ',' gateOr			{ $$ = $1->addNext($3); }
+	|	gateOrList ',' gateOr			{ $$ = $1->addNext($3); }
 	;
 gateNorList:	gateNor 				{ $$ = $1; }
-	|	gateNor ',' gateNor			{ $$ = $1->addNext($3); }
+	|	gateNorList ',' gateNor			{ $$ = $1->addNext($3); }
 	;
 gateXorList:	gateXor 				{ $$ = $1; }
-	|	gateXor ',' gateXor			{ $$ = $1->addNext($3); }
+	|	gateXorList ',' gateXor			{ $$ = $1->addNext($3); }
 	;
 gateXnorList:	gateXnor 				{ $$ = $1; }
-	|	gateXnor ',' gateXnor			{ $$ = $1->addNext($3); }
+	|	gateXnorList ',' gateXnor		{ $$ = $1->addNext($3); }
 	;
 
 gateBuf: 	gateIdE instRangeE '(' varRefDotBit ',' expr ')'		{ $$ = new AstAssignW ($3,$4,$6); $$->allowImplicit(true); }

test_regress/t/t_gate_basic.v

@@ -15,8 +15,9 @@ module t (/*AUTOARG*/
    reg [31:0] a;
    reg [31:0] b;
    
-   wire [1:0] bf;  buf   BF0 (bf[0], a[0]),
-		         BF1 (bf[1], a[1]);
+   wire [2:0] bf;  buf   BF0 (bf[0], a[0]),
+		         BF1 (bf[1], a[1]),
+		         BF2 (bf[2], a[2]);
 
    // verilator lint_off IMPLICIT
    not   NT0 (nt0, a[0]);
@@ -60,8 +61,7 @@ module t (/*AUTOARG*/
 	 if (cyc==2) begin
 	    a <= 32'h529ab56f;
 	    b <= 32'h7835a237;
-	    if (bf[0] !== 1'b0) $stop;
-	    if (bf[1] !== 1'b0) $stop;
+	    if (bf !== 3'b100) $stop;
 	    if (nt0 !== 1'b1) $stop;
 	    if (an0 !== 1'b0) $stop;
 	    if (nd0 !== 1'b1) $stop;
@@ -72,8 +72,7 @@ module t (/*AUTOARG*/
 	    if (ba != 32'h18f6b034) $stop;
 	 end
 	 if (cyc==3) begin
-	    if (bf[0] !== 1'b1) $stop;
-	    if (bf[1] !== 1'b1) $stop;
+	    if (bf !== 3'b111) $stop;
 	    if (nt0 !== 1'b0) $stop;
 	    if (an0 !== 1'b1) $stop;
 	    if (nd0 !== 1'b0) $stop;

test_regress/t/t_pp_display.pl

@@ -16,11 +16,11 @@ execute (
 'pre thrupre thrumid thrupost post: "right side"
 left side: "right side"
 left side : "right side "
-left_side : "left_side "
-na : "left_side "
-prep ( midp1 left_side midp2 ( outp ) ) : "left_side "
+left_side : "right_side "
+na : "right_side "
+prep ( midp1 left_side midp2 ( outp ) ) : "right_side "
 na: "nana"
-left_side left_side : "left_side left_side "
+`ls `rs : "`ls `rs "
 : ""
 left side: "right side"
 left side  : "right side  "

test_regress/t/t_pp_display.v

@@ -13,8 +13,8 @@ module t;
    add2 add2 (d2,o2);
 
 `define ls left_side
-`define rs left_side
-`define noarg  na
+`define rs right_side
+`define noarg  na//note extra space
 `define thru(x) x
 `define thruthru `ls `rs	// Doesn't expand
 `define msg(x,y) `"x: `\`"y`\`"`"

test_regress/t/t_preproc.out

@@ -155,13 +155,26 @@ wire  tmp_d2  = d2 ;  wire  tmp_o2  = tmp_d2  + 1;  assign o2  = tmp_o2  ;
    generate for (i=0; i<(3); i=i+1) begin        psl cover {  m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1";        psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] &  m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1";     end endgenerate	
 
 
+ 
+ 
+ 
+ 
+ 
+ 
+ 
+
+begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end
+begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end
+begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end 
+
+
 
 
  
  
    
 
-`line 117 "t/t_preproc.v" 0
+`line 130 "t/t_preproc.v" 0
 
-Line_Preproc_Check 118
-`line 119 "t/t_preproc.v" 2
+Line_Preproc_Check 131
+`line 132 "t/t_preproc.v" 2

test_regress/t/t_preproc.v

@@ -108,6 +108,19 @@ assign c = tmp_``c ;
 
    `check(m5kc_fcl, 3, _ctl_mvldx_m1, `CK_fr,	`MF._ctl_mvldx_m1)	// ignorecmt
 
+// macro call with define that has comma
+`define REG_H   6
+`define REG_L   7
+`define _H      regs[`REG_H]
+`define _L      regs[`REG_L]
+`define _HL     {`_H, `_L}
+`define EX_WRITE(ad, da)      begin addr <= (ad); wdata <= (da); wr <= 1; end
+`define EX_READ(ad)           begin addr <= (ad); rd <= 1; end
+
+`EX_READ((`_HL + 1)) and `EX_WRITE((`_HL), rdata)
+`EX_READ(`_HL + 1)
+`EX_WRITE(`_HL, rdata) 
+
 //===========================================================================
 // Ifdef
 

test_regress/t/t_preproc_ifdef.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_preproc_ifdef.v

@@ -0,0 +1,44 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+   integer num;
+   initial begin
+      num = 0;
+
+`define EMPTY_TRUE
+`ifndef EMPTY_TRUE
+  `error "Empty is still true"
+`endif
+
+`define A
+`ifdef A	$display("1A"); num = num + 1;
+ `ifdef C	$stop;
+ `elsif A	$display("2A"); num = num + 1;
+  `ifdef C	$stop;
+  `elsif B	$stop;
+  `else		$display("3A"); num = num + 1;
+  `endif
+ `else		$stop;
+ `endif
+ `elsif B	$stop;
+  `ifdef A	$stop;
+  `elsif A	$stop;
+  `else
+  `endif
+`elsif C	$stop;
+`else		$stop;
+`endif
+      if (num == 3) begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+      else begin
+	 $write("%%Error: Bad count: %d\n", num);
+	 $stop;
+      end
+   end
+endmodule