Version bump

git-svn-id: file://localhost/svn/verilator/trunk/verilator@957 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -3,6 +3,14 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.654 10/18/2007
+
+**** Don't exit early if many warnings but no errors are found. [Stan Mayer]
+
+**** Fix parsing module #(parameter x,y) declarations. [Oleg Rodionov]
+
+**** Fix parsing system functions with empty parens. [Oleg Rodionov]
+
 * Verilator 3.653 8/1/2007
 
 **** Support SystemVerilog ==? and !=? operators.

TODO

@@ -25,6 +25,7 @@ Features:
 	Coverage
 		Points should be per-scope like everything else rather then per-module
 		Expression coverage (see notes)
+	Constant functions for widths, etc, IE   "input [log2(PARAM):0] xx;"
 	More Verilog 2001 Support
 		(* *) Attributes  (just ignore -- preprocessor?)
 		Real numbers (NEVER)

bin/verilator

@@ -2001,6 +2001,17 @@ the "verilator" define for you, so just wrap the code in a ifndef region:
       Something_Verilator_Dislikes;
    `endif
 
+=item Why do I get "unexpected `do'" or "unexpected `bit'" errors?
+
+Do, bit, ref, and other words are now SystemVerilog keywords.  You should
+change your code to not use them to insure it works with newer tools.
+Alternatively, surround them by the Verilog 2005/SystemVerilog
+begin_keywords pragma to indicate Verilog 2001 code.
+
+   `begin_keywords "1364-2001"
+      integer bit; initial bit = 1;
+   `end_keywords
+
 =item How do I prevent my assertions from firing during reset?
 
 Call Verilated::assertOn(false) before you first call the model, then turn

src/V3Error.cpp

@@ -190,14 +190,12 @@ string V3Error::lineStr (const char* filename, int lineno) {
 
 void V3Error::incWarnings() {
     s_warnCount++;
-    if (errorOrWarnCount() == MAX_ERRORS) {  // Not >= as would otherwise recurse
-	v3fatal ("Exiting due to too many errors encountered\n");
-    }
+    // We don't exit on a lot of warnings.
 }
 
 void V3Error::incErrors() {
     s_errCount++;
-    if (errorOrWarnCount() == MAX_ERRORS) {  // Not >= as would otherwise recurse
+    if (errorCount() == MAX_ERRORS) {  // Not >= as would otherwise recurse
 	v3fatal ("Exiting due to too many errors encountered\n");
     }
 }

src/config_build.h.in

@@ -24,7 +24,7 @@
 //**********************************************************************
 //**** Version and host name
 
-#define DTVERSION	"Verilator 3.653 8/1/2007"
+#define DTVERSION	"Verilator 3.654 8/1/2007"
 
 //**********************************************************************
 //**** Functions

src/verilog.l

@@ -568,6 +568,12 @@ escid	\\[^ \t\f\r\n]+
   "~&"			{yylval.fileline = CRELINE(); return yP_NAND;}
   "~|"			{yylval.fileline = CRELINE(); return yP_NOR;}
   "->"			{yylval.fileline = CRELINE(); return yP_MINUSGT;}
+  "=>"                  {yylval.fileline = CRELINE(); return yP_EQGT; }
+  "*>"                  {yylval.fileline = CRELINE(); return yP_ASTGT; }
+  "+=>"                 {yylval.fileline = CRELINE(); return yP_PLUSEQGT; }
+  "+*>"                 {yylval.fileline = CRELINE(); return yP_PLUSASTGT; }
+  "-=>"                 {yylval.fileline = CRELINE(); return yP_MINUSEQGT; }
+  "-*>"                 {yylval.fileline = CRELINE(); return yP_MINUSASTGT; }
 }
 
   /* Verilog 2001 Operators */

src/verilog.y

@@ -248,6 +248,12 @@ class AstSenTree;
 
 %token<fileline>	yP_PLUSCOLON	"+:"
 %token<fileline>	yP_MINUSCOLON	"-:"
+%token<fileline>	yP_EQGT		"=>"
+%token<fileline>	yP_ASTGT	"*>"
+%token<fileline>	yP_PLUSEQGT	"+=>"
+%token<fileline>	yP_PLUSASTGT	"+*>"
+%token<fileline>	yP_MINUSEQGT	"-=>"
+%token<fileline>	yP_MINUSASTGT	"-*>"
 
 %token<fileline>	yPSL_BRA	"{"
 %token<fileline>	yPSL_KET	"}"
@@ -290,7 +296,7 @@ class AstSenTree;
 %type<nodep>	modPortsE portList port
 %type<nodep>	portV2kArgs portV2kList portV2kSecond portV2kSig
 %type<nodep>	portV2kDecl ioDecl varDecl
-%type<nodep>	modParDecl modParList modParE
+%type<nodep>	modParArgs modParSecond modParDecl modParList modParE
 %type<nodep>	modItem modItemList modItemListE modOrGenItem
 %type<nodep>	genItem genItemList genItemBegin genItemBlock genTopBlock genCaseListE genCaseList
 %type<nodep>	dlyTerm
@@ -375,12 +381,20 @@ modHdr:		yMODULE { V3Parse::s_trace=v3Global.opt.trace();}
 
 modParE:	/* empty */				{ $$ = NULL; }
 	|	'#' '(' ')'				{ $$ = NULL; }
-	|	'#' '(' modParList ')'			{ $$ = $3; }
-	|	'#' '(' modParList ';' ')'		{ $$ = $3; }
+	|	'#' '(' modParArgs ')'			{ $$ = $3; }
 	;
 
-modParList:	modParDecl				{ $$ = $1; }
-	|	modParList ';' modParDecl 		{ $$ = $1->addNext($3); }
+modParArgs:	modParDecl				{ $$ = $1; }
+	|	modParDecl ',' modParList		{ $$ = $1->addNext($3); }
+	;
+
+modParList:	modParSecond				{ $$ = $1; }
+	|	modParList ',' modParSecond 		{ $$ = $1->addNext($3); }
+	;
+
+// Called only after a comma in a v2k list, to allow parsing "parameter a,b, parameter x"
+modParSecond:	modParDecl				{ $$ = $1; }
+	|	param					{ $$ = $1; }
 	;
 
 modPortsE:	/* empty */					{ $$ = NULL; }
@@ -440,7 +454,7 @@ varDecl:	varRESET varReg     varSignedE regrangeE  regsigList ';'	{ $$ = $5; }
 	|	varRESET varGenVar  varSignedE            regsigList ';'	{ $$ = $4; }
 	;
 
-modParDecl:	varRESET varGParam  varSignedE regrangeE   paramList 	{ $$ = $5; }  /* No semicolon*/
+modParDecl:	varRESET varGParam  varSignedE regrangeE   param 	{ $$ = $5; }
 	;
 
 varRESET:	/* empty */ 				{ VARRESET(); }
@@ -779,24 +793,24 @@ stmt:		';'					{ $$ = NULL; }
 	|	'{' concIdList '}' '=' delayE expr ';'  { $$ = new AstAssign($4,$2,$6); }
 	|	yD_C '(' cStrList ')' ';'		{ $$ = (v3Global.opt.ignc() ? NULL : new AstUCStmt($1,$3)); }
 	|	yD_FCLOSE '(' varRefDotBit ')' ';'	{ $$ = new AstFClose($1, $3); }
-	|	yD_FINISH ';'				{ $$ = new AstFinish($1); }
-	|	yD_STOP ';'				{ $$ = new AstStop($1); }
+	|	yD_FINISH parenE ';'			{ $$ = new AstFinish($1); }
+	|	yD_STOP parenE ';'			{ $$ = new AstStop($1); }
 	|	yVL_COVER_OFF				{ $$ = new AstPragma($1,AstPragmaType::COVERAGE_BLOCK_OFF); }
 	|	stateCaseForIf				{ $$ = $1; }
 	|	taskRef ';' 				{ $$ = $1; }
 
-	|	yD_DISPLAY  ';'							{ $$ = new AstDisplay($1,AstDisplayType::DISPLAY,"", NULL,NULL); }
+	|	yD_DISPLAY  parenE ';'						{ $$ = new AstDisplay($1,AstDisplayType::DISPLAY,"", NULL,NULL); }
 	|	yD_DISPLAY  '(' yaSTRING commaEListE ')' ';'			{ $$ = new AstDisplay($1,AstDisplayType::DISPLAY,*$3,NULL,$4); }
 	|	yD_WRITE    '(' yaSTRING commaEListE ')' ';'			{ $$ = new AstDisplay($1,AstDisplayType::WRITE,  *$3,NULL,$4); }
 	|	yD_FDISPLAY '(' varRefDotBit ',' yaSTRING commaEListE ')' ';' 	{ $$ = new AstDisplay($1,AstDisplayType::DISPLAY,*$5,$3,$6); }
 	|	yD_FWRITE   '(' varRefDotBit ',' yaSTRING commaEListE ')' ';'	{ $$ = new AstDisplay($1,AstDisplayType::WRITE,  *$5,$3,$6); }
-	|	yD_INFO	    ';'							{ $$ = new AstDisplay($1,AstDisplayType::INFO,   "", NULL,NULL); }
+	|	yD_INFO	    parenE ';'						{ $$ = new AstDisplay($1,AstDisplayType::INFO,   "", NULL,NULL); }
 	|	yD_INFO	    '(' yaSTRING commaEListE ')' ';'			{ $$ = new AstDisplay($1,AstDisplayType::INFO,   *$3,NULL,$4); }
-	|	yD_WARNING  ';'							{ $$ = new AstDisplay($1,AstDisplayType::WARNING,"", NULL,NULL); }
+	|	yD_WARNING  parenE ';'						{ $$ = new AstDisplay($1,AstDisplayType::WARNING,"", NULL,NULL); }
 	|	yD_WARNING  '(' yaSTRING commaEListE ')' ';'			{ $$ = new AstDisplay($1,AstDisplayType::WARNING,*$3,NULL,$4); }
-	|	yD_ERROR    ';'							{ $$ = V3Parse::createDisplayError($1); }
+	|	yD_ERROR    parenE ';'						{ $$ = V3Parse::createDisplayError($1); }
 	|	yD_ERROR    '(' yaSTRING commaEListE ')' ';'			{ $$ = new AstDisplay($1,AstDisplayType::ERROR,  *$3,NULL,$4);   $$->addNext(new AstStop($1)); }
-	|	yD_FATAL    ';'							{ $$ = new AstDisplay($1,AstDisplayType::FATAL,  "", NULL,NULL); $$->addNext(new AstStop($1)); }
+	|	yD_FATAL    parenE ';'						{ $$ = new AstDisplay($1,AstDisplayType::FATAL,  "", NULL,NULL); $$->addNext(new AstStop($1)); }
 	|	yD_FATAL    '(' expr ')' ';'					{ $$ = new AstDisplay($1,AstDisplayType::FATAL,  "", NULL,NULL); $$->addNext(new AstStop($1)); }
 	|	yD_FATAL    '(' expr ',' yaSTRING commaEListE ')' ';'		{ $$ = new AstDisplay($1,AstDisplayType::FATAL,  *$5,NULL,$6);   $$->addNext(new AstStop($1)); }
 
@@ -895,6 +909,10 @@ funcVar: 	ioDecl					{ $$ = $1; }
 	|	yVL_NO_INLINE_TASK			{ $$ = new AstPragma($1,AstPragmaType::NO_INLINE_TASK); }
 	;
 
+parenE:		/* empty */				{ }
+	|	'(' ')'					{ }
+	;
+
 //************************************************
 // Expressions
 
@@ -1120,6 +1138,9 @@ specifyJunk:	dlyTerm 	{} /* ignored */
 	|	yPSL_KET {}
 	|	yP_OR_MINUS_GT {}
 	|	yP_OR_EQ_GT {}
+	|	yP_EQGT {}	| yP_ASTGT {}
+	|	yP_PLUSEQGT {}	| yP_PLUSASTGT {}
+	|	yP_MINUSEQGT {} | yP_MINUSASTGT {}
 
 	|	error {}
 	;

test_regress/t/t_param_named.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -11,7 +11,10 @@ module t (/*AUTOARG*/
    parameter PAR = 3;
    input clk;
 
+`ifdef verilator
+   // Else it becomes a localparam, per IEEE 4.10.1, but we don't check it
    defparam m3.FROMDEFP = 19;
+`endif
 
    m3 #(.P3(PAR),
 	.P2(2))
@@ -29,14 +32,12 @@ module t (/*AUTOARG*/
 endmodule
 
 module m3
-`ifdef verilator
   #(
-    parameter  UNCH = 99;
-    parameter  P1 = 10;
+    parameter  UNCH = 99,
+    parameter  P1 = 10,
     parameter  P2 = 20,
-               P3 = 30;
+               P3 = 30
     )
-`endif
     (/*AUTOARG*/
      // Inputs
      clk
@@ -44,13 +45,6 @@ module m3
    input       clk;
    localparam  LOC = 13;
 
-`ifndef verilator   // Vcs not compliant yet
-   parameter   UNCH = 99;
-   parameter   P1 = 10;
-   parameter   P2 = 20;
-   parameter   P3 = 30;
-`endif
-
    parameter   FROMDEFP = 11;
 
    initial begin
@@ -61,6 +55,8 @@ module m3
       if (P1 !== 10) $stop;
       if (P2 !== 2) $stop;
       if (P3 !== 3) $stop;
+`ifdef verilator
       if (FROMDEFP !== 19) $stop;
+`endif
    end
 endmodule