Test fix

git-svn-id: file://localhost/svn/verilator/trunk/verilator@825 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -3,7 +3,11 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
-* Verilator 3.621 10/11/2006
+* Verilator 3.622 10/17/2006 Stable
+
+**** Fix --skip-identical without --debug, broken in 3.621.  [Andy Meier]
+
+* Verilator 3.621 10/11/2006 Beta
 
 **   Add /*verilator no_inline_task*/ to prevent over-expansion. [Eugene Weber]
 
@@ -17,7 +21,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix core dump on printing error when not under --debug.  [Allan Cochrane]
 
-* Verilator 3.620 10/04/2006
+* Verilator 3.620 10/04/2006 Stable
 
 ***  Support simple inout task ports.  [Eugene Weber]
 

bin/verilator

@@ -407,7 +407,7 @@ compatibility.
 
 =item --psl
 
-Enable PSL parsing.  Without this switch, psl meta-comments are ignored.
+Enable PSL parsing.  Without this switch, PSL meta-comments are ignored.
 See the --assert flag to enable all assertions, and --coverage-user to
 enable functional coverage.
 
@@ -609,7 +609,7 @@ Then we convert the SystemPerl output to SystemC.
     $SYSTEMPERL/sp_preproc --preproc *.sp
 
 (You can also skip the above sp_preproc by getting pure SystemC from
-verilator by replacing the verilator --sp flag in the previous step with
+Verilator by replacing the verilator --sp flag in the previous step with
 -sc.)
 
 We then can compile it
@@ -938,7 +938,7 @@ call C++ functions from your Verilog code.
 String arguments will be put directly into the output C++ code.  Expression
 arguments will have the code to evaluate the expression inserted.  Thus to
 call a C++ function, $c("func(",a,")") will result in 'func(a)' in the
-output C++ code.  For input arguments, rather then hardcoding variable
+output C++ code.  For input arguments, rather then hard-coding variable
 names in the string $c("func(a)"), instead pass the variable as an
 expression $c("func(",a,")").  This will allow the call to work inside
 Verilog functions where the variable is flattened out, and also enable
@@ -1279,7 +1279,7 @@ appropriate width.
 $display and friends must have a constant format string as the first
 argument (as with C's printf), you cannot simply list variables standalone.
 
-=head1 ERRORS
+=head1 ERRORS AND WARNINGS
 
 Warnings may be disabled in two ways.  First, when the warning is
 printed it will include a warning code.  Simply surround the offending
@@ -1289,13 +1289,13 @@ line with a warn_off/warn_on pair:
 	if (`DEF_THAT_IS_EQ_ZERO <= 3) $stop;
 	// verilator lint_on UNSIGNED
 
-They may also be globally disabled by invoking Verilator with the
-C<-Wno-I<warning>> switch.  This should be avoided, as it removes
-all checking across the designs, and prevents other users from
-compiling your code without knowing the magic set of disables needed
-to successfully compile your design.
+Warnings may also be globally disabled by invoking Verilator with the
+C<-Wno-I<warning>> switch.  This should be avoided, as it removes all
+checking across the designs, and prevents other users from compiling your
+code without knowing the magic set of disables needed to successfully
+compile your design.
 
-Warnings:
+List of all warnings:
 
 =over 4
 
@@ -1364,6 +1364,29 @@ Warns that the specified signal comes from multiple always blocks.  This is
 often unsupported by synthesis tools, and is considered bad style.  It will
 also cause longer runtimes due to reduced optimizations.
 
+=item TASKNSVAR
+
+Error when a call to a task or function has a output from that task tied to
+a non-simple signal.  Instead connect the task output to a temporary signal
+of the appropriate width, and use that signal to set the appropriate
+expression as the next statement.  For example:
+
+      task foo; output sig; ... endtask
+      always @* begin
+           foo(bus_we_select_from[2]);   // Will get TASKNSVAR error
+      end
+
+Change this to:
+
+      reg foo_temp_out;
+      always @* begin
+           foo(foo_temp_out);
+           bus_we_select_from[2] = foo_temp_out;
+      end
+
+Verilator doesn't do this conversion for you, as some more complicated
+cases would result in simulator mismatches.
+
 =item UNDRIVEN
 
 Warns that the specified signal is never sourced.
@@ -1389,11 +1412,11 @@ may be only one particular usage of a multiply instantiated block.  The
 construct should be cleaned up to improve runtime; two times better
 performance may be possible by fixing these warnings.
 
-Unlike UNOPT this occurs after netlist flattening, and indicates a more
-basic problem, as the less obvious case described under UNOPT does not
-apply.
+Unlike the UNOPT warning, this occurs after netlist flattening, and
+indicates a more basic problem, as the less obvious case described under
+UNOPT does not apply.
 
-Often this is caused by logic that isn't truly circular as viewed by
+Often UNOPTFLAT is caused by logic that isn't truly circular as viewed by
 synthesis which analyzes interconnection per-bit, but is circular to
 simulation which analyzes per-bus:
 
@@ -1401,12 +1424,25 @@ simulation which analyzes per-bus:
 
 This statement needs to be evaluated multiple times, as a change in
 "shift_in" requires "x" to be computed 3 times before it becomes stable.
-For significantly better performance, split this into 2 separate signals:
+For significantly better performance, split this into 2 separate signals,
+and then if necessary generate the original signal:
 
       wire [2:1] x_21 = x[1:0];
       wire [0:0] x_0  = shift_in;
+      wire [2:0] x = {x_21, x_0};
 
-This warning may also be due to clock enables.  To fix these, use the
+This logic needs to be evaluated only once.  These sort of changes may also
+speed up your traditional event driven simulator, as it will result in
+fewer events per cycle.
+
+The most complicated UNOPTFLAT path we've seen was due to low bits of a bus
+being generated from an always statement that consumed high bits of the
+same bus processed by another series of always blocks.  The fix is the
+same; split it into two separate signals, then create the bus from the two
+separate signals.
+
+The UNOPTFLAT warning may also be due to clock enables, identified from the
+reported path going through a clock gating cell.  To fix these, use the
 clock_enable meta comment described above.
 
 =item UNSIGNED
@@ -1464,8 +1500,8 @@ that is not yet supported in Verilator.  See the Limitations chapter.
 =item Verilated model didn't converge
 
 Verilator sometimes has to evaluate combinatorial logic multiple times,
-usually around code where a UNOPT warning was issued, but disabled.  For
-example:
+usually around code where a UNOPTFLAT warning was issued, but disabled.
+For example:
 
    always @ (a)  b=~a;
    always @ (b)  a=b

src/V3EmitCBase.h

@@ -109,7 +109,7 @@ public:
     bool optSystemPerl() { return v3Global.opt.systemPerl(); }
     static string symClassName() { return v3Global.opt.prefix()+"__Syms"; }
     static string symClassVar()  { return symClassName()+"* __restrict vlSymsp"; }
-    static string symTopAssign() { return v3Global.opt.prefix()+"* __restrict vlTOPp = vlSymsp->TOPp;"; }
+    static string symTopAssign() { return v3Global.opt.prefix()+"* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;"; }
     static string modClassName(AstModule* modp) {	// Return name of current module being processed
 	if (modp->isTop()) {
 	    return v3Global.opt.prefix();

src/V3Error.cpp

@@ -92,7 +92,7 @@ void FileLine::lineDirective(const char* textp) {
 
 bool FileLine::warnOff(const string& msg, bool flag) {
     V3ErrorCode code (msg.c_str());
-    if (code == V3ErrorCode::ERROR) {
+    if (code < V3ErrorCode::FIRST_WARN) {
 	return false;
     } else {
 	warnOff(code, flag);
@@ -203,8 +203,9 @@ void V3Error::abortIfErrors() {
 string V3Error::msgPrefix(V3ErrorCode code) {
     if (code==V3ErrorCode::SUPPRESS) return "-arning-suppressed: ";
     else if (code==V3ErrorCode::FATAL) return "%Error: ";
-    else if (code==V3ErrorCode::ERROR
-	     || s_pretendError[code]) return "%Error: ";
+    else if (code==V3ErrorCode::ERROR) return "%Error: ";
+    else if (code<V3ErrorCode::FIRST_WARN
+	     || s_pretendError[code]) return "%Error-"+(string)code.ascii()+": ";
     else return "%Warning-"+(string)code.ascii()+": ";
 }
 

src/V3Error.h

@@ -34,9 +34,12 @@ public:
     enum en {
 	SUPPRESS,	// Warning suppressed by user
 	FATAL,		// Kill the program
-	ERROR,		// Error out, can't suppress
+	ERROR,		// General error out, can't suppress
+	// Error codes:
+	TASKNSVAR,	// Error: Task I/O not simple
 	// Warning codes:
 	FIRST_WARN,	// Just a code so the program knows where to start warnings
+	//
 	BLKANDNBLK,	// Blocked and non-blocking assignments to same variable
 	CASEINCOMPLETE,	// Case statement has missing values
 	CASEOVERLAP,	// Case statements overlap
@@ -67,6 +70,7 @@ public:
 	const char* names[] = {
 	    // Leading spaces indicate it can't be disabled.
 	    " SUPPRESS", " FATAL", " ERROR",
+	    "TASKNSVAR",
 	    " FIRST_WARN",
 	    "BLKANDNBLK",
 	    "CASEINCOMPLETE", "CASEOVERLAP", "CASEX", "CMPCONST",
@@ -82,7 +86,7 @@ public:
     bool dangerous() const { return ( m_e==COMBDLY );};
     // Warnings we'll present to the user as errors
     // Later -Werror- options may make more of these.
-    bool pretendError() const { return ( m_e==BLKANDNBLK || m_e==IMPURE );};
+    bool pretendError() const { return ( m_e==BLKANDNBLK || m_e==IMPURE); };
   };
   inline bool operator== (V3ErrorCode lhs, V3ErrorCode rhs) { return (lhs.m_e == rhs.m_e); }
   inline bool operator== (V3ErrorCode lhs, V3ErrorCode::en rhs) { return (lhs.m_e == rhs); }

src/V3File.h

@@ -42,6 +42,9 @@ public:
     }
     static ofstream* new_ofstream(const string& filename, bool append=false) {
 	addTgtDepend(filename);
+	return new_ofstream_nodepend (filename, append);
+    }
+    static ofstream* new_ofstream_nodepend(const string& filename, bool append=false) {
 	if (append) {
 	    return new ofstream(filename.c_str(), ios::app);
 	} else {

src/V3Options.h

@@ -141,6 +141,7 @@ class V3Options {
     bool trace() const { return m_trace; }
     bool traceDups() const { return m_traceDups; }
     bool outFormatOk() const { return m_outFormatOk; }
+    bool keepTempFiles() const { return (V3Error::debugDefault()!=0); }
     bool pins64() const { return m_pins64; }
     bool profileCFuncs() const { return m_profileCFuncs; }
     bool psl() const { return m_psl; }

src/V3PreShell.cpp

@@ -79,6 +79,8 @@ protected:
 	ostream* osp;
 	if (v3Global.opt.preprocOnly()) {
 	    osp = &cout;
+	} else if (!v3Global.opt.keepTempFiles()) {  // Must match unlink rule in V3Read.cpp
+	    osp = ofp = V3File::new_ofstream_nodepend(vppFilename);
 	} else {
 	    osp = ofp = V3File::new_ofstream(vppFilename);
 	}

src/V3Read.cpp

@@ -92,7 +92,7 @@ void V3Read::readFile(FileLine* fileline, const string& modfilename, bool inLibr
 	lexFile (vppfilename, modfilename);
     }
 
-    if (!V3Error::debugDefault()) {
+    if (!v3Global.opt.keepTempFiles()) {  // Must match new_ofstream_nodepend rule in V3PreShell.cpp
 	unlink (vppfilename.c_str());
     }
 }

src/V3Task.cpp

@@ -348,7 +348,7 @@ private:
 				AstVarScope* localVscp = varrefp->varScopep(); if (!localVscp) varrefp->v3fatalSrc("Null var scope");
 				portp->user2p(localVscp);
 			    } else {
-				pinp->v3error("Unsupported: Function/task input argument is not simple variable");
+				pinp->v3warn(TASKNSVAR,"Unsupported: Function/task input argument is not simple variable");
 			    }
 			}
 			else if (portp->isOutput() && outvscp) {
@@ -360,7 +360,7 @@ private:
 			    if (AstVarRef* varrefp = pinp->castVarRef()) {
 				varrefp->lvalue(true);
 			    } else {
-				pinp->v3error("Unsupported: Task output pin connected to non-variable");
+				pinp->v3warn(TASKNSVAR,"Unsupported: Task output pin connected to non-variable");
 			    }
 			    // Even if it's referencing a varref, we still make a temporary
 			    // Else task(x,x,x) might produce incorrect results
@@ -436,7 +436,7 @@ private:
 			    if (pinp->castVarRef()) {
 				// Connect to this exact variable
 			    } else {
-				pinp->v3error("Unsupported: Function/task input argument is not simple variable");
+				pinp->v3warn(TASKNSVAR,"Unsupported: Function/task input argument is not simple variable");
 			    }
 			}
 			else if (portp->isOutput()) {
@@ -445,7 +445,7 @@ private:
 			    if (AstVarRef* varrefp = pinp->castVarRef()) {
 				varrefp->lvalue(true);
 			    } else {
-				pinp->v3error("Unsupported: Task output pin connected to non-variable");
+				pinp->v3warn(TASKNSVAR,"Unsupported: Task output pin connected to non-variable");
 			    }
 			}
 		    }

src/config.h.in

@@ -24,7 +24,7 @@
 //**********************************************************************
 //**** Version and host name
 
-#define DTVERSION	"Verilator 3.621 10/11/2006"
+#define DTVERSION	"Verilator 3.622 10/17/2006"
 
 //**********************************************************************
 //**** Functions

test_c/Makefile_obj

@@ -20,8 +20,8 @@ include Vtop.mk
 CPPFLAGS += -DVL_DEBUG=1
 ifeq ($(VERILATOR_AUTHOR_SITE),1)	# Local... Else don't burden users
 CPPFLAGS += -DVL_THREADED=1
-CPPFLAGS += -W
-CPPFLAGS += -Werror
+CPPFLAGS += -W -Werror -Wall
+#CPPFLAGS += -Wno-unused-variable	# Instead, add VL_ATTR_UNUSED in gen'ed code
 #CPPFLAGS += -pedantic-errors
 endif
 

test_regress/t/t_flag_skipidentical.pl

@@ -0,0 +1,30 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+if ($Last_Self->{v3}) {
+    compile ();
+
+    my $outfile = "obj_dir/V".$Last_Self->{name}.".cpp";
+    my @oldstats = stat($outfile);
+    print "Old mtime=",$oldstats[9],"\n";
+    $oldstats[9] or $Last_Self->error("No output file found: $outfile\n");
+
+    sleep (1);  # Or else it might take < 1 second to compile and see no diff.
+
+    compile ();
+
+    my @newstats = stat($outfile);
+    print "New mtime=",$newstats[9],"\n";
+
+    ($oldstats[9] == $newstats[9])
+	or $Last_Self->error("--skip-identical was ignored -- recompiled\n");
+}
+
+ok(1);
+1;

test_regress/t/t_flag_skipidentical.v

@@ -0,0 +1,9 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2006 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+
+endmodule

test_regress/t/t_flag_werror_bad2.pl

@@ -13,7 +13,7 @@ compile (
 	 fails=>$Last_Self->{v3},
 	 verilator_flags=> [qw(-sp -Werror-WIDTH)],
 	 expect=>
-'%Error: t/t_flag_werror.v:\d+: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS.s CONST generates 6 bits.
+'%Error-WIDTH: t/t_flag_werror.v:\d+: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS.s CONST generates 6 bits.
 %Error: Exiting due to',
 	 ) if $Last_Self->{v3};
 

test_regress/t/t_func_bad.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -13,7 +13,7 @@ compile (
 '%Error: t/t_func_bad.v:\d+: Too few arguments in function call
 %Error: t/t_func_bad.v:\d+: Too many arguments in function call
 %Error: t/t_func_bad.v:\d+: Too few arguments in function call
-%Error: t/t_func_bad.v:\d+: Unsupported: Task output pin connected to non-variable
+%Error-TASKNSVAR: t/t_func_bad.v:\d+: Unsupported: Task output pin connected to non-variable
 %Error: t/t_func_bad.v:\d+: Outputs not allowed in function declarations
 %Error: Exiting due to',
 	 );

test_regress/t/t_math_div.v

@@ -39,7 +39,6 @@ module t (/*AUTOARG*/
 	    a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
 	    divisor <= 61'h1238123771;
 	    a[60] <= 1'b0; divisor[60] <= 1'b0;  // Unsigned
-//$display("FIX");
 	    if (qq!==61'h00000403ad81c0da) $stop;
 	    if (rq!==61'h00000000000090ec) $stop;
 	    if (qqs!==61'h00000403ad81c0da) $stop;

test_sp/Makefile_obj

@@ -21,6 +21,9 @@ CPPFLAGS += -DUTIL_PRINTF=sp_log_printf
 CPPFLAGS += -Wno-deprecated
 CPPFLAGS += $(SYSTEMC_CXX_FLAGS)
 CPPFLAGS += $(OPT)
+ifeq ($(VERILATOR_AUTHOR_SITE),1)	# Local... Else don't burden users
+#CPPFLAGS += -W -Wall -Wno-char-subscripts -Wno-unused-parameter -Wno-unused-variable -Wno-uninitialized -Werror
+endif
 
 LDFLAGS += $(SYSTEMC_CXX_FLAGS)