Veripool API Bot
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ce4d35aa85
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Verilog format
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2026-03-03 07:21:24 -05:00 |
Wilson Snyder
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7c6c6a684b
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Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
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2026-01-26 20:24:34 -05:00 |
Iztok Jeras
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2aa6a229ca
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Change range order warning from LITENDIAN to ASCRANGE (#4010)
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2023-03-20 20:44:11 -04:00 |
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Wilson Snyder
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975c1b39a9
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Fix little endian packed array pattern assignment (#2795).
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2021-02-20 20:29:28 -05:00 |
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Wilson Snyder
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882b310897
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Fix little endian packed array counting (#2499).
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2020-12-13 16:23:59 -05:00 |