Veripool API Bot
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1f67080a1f
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Tests: Verilog format
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2026-03-09 21:39:16 -04:00 |
Wilson Snyder
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7c6c6a684b
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Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
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2026-01-26 20:24:34 -05:00 |
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Wilson Snyder
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29ed866061
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Fix range inheritance on port without data type (#2753).
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2021-03-11 19:22:19 -05:00 |
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Wilson Snyder
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e88dff6929
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Tests: Improve t_mod_interface_array4
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2021-03-11 13:32:38 -05:00 |
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Wilson Snyder
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fd6edd90bc
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Fix little endian interface pin swizzling (#2475).
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2021-02-20 22:11:20 -05:00 |