Commit Graph

9 Commits

Author SHA1 Message Date
Geza Lore 86c56e8e14 Fix true cycle detection in DFG 2025-08-05 15:04:07 +01:00
Geza Lore 53332ae03e
Unify the two DFG cycle finding algorithms. (#6262)
Both V3DfgBreakCycles.cpp and V3DfgDecomposition.cpp used to contain an
implementation of the same algorithm to color strongly connected
components. Now there is only one, and it lives in V3DfgColorSCCs.cpp.
2025-08-05 13:03:30 +01:00
Geza Lore 504884b7d5
Refactor DFG context objects (#6232)
- Move All DFG context objects to V3DfgContext.h
- Add separate object for ast2dfg and dfg2ast passes
- Factor out commonalities

No functional change
2025-07-26 20:37:01 +01:00
Geza Lore 2be257369a
Fix component numbers of new Vertices in V3DfgBreakCycles (#6228)
Fix component numbers of new Vertices in V3DfgBreakCycles

Fixes part of #6225
2025-07-24 15:31:09 +01:00
Geza Lore 9f04ee68c8
Optimize combinational cycles through arrays in DFG (#6210)
Extending V3DfgBreakCycles to handle common cases involving unpacked
arrays.
2025-07-22 08:23:45 +01:00
Geza Lore 7401a8a43a
Refactor DFG IndependentBits analysis to work for any vertex. (#6209)
This used to be restricted to variable vertices, but now can handle
arbitrary circular vertices that represent packed values. It also
converges faster than the earlier version. Prep for resolving loops
through arrays.
2025-07-21 19:57:02 +01:00
Geza Lore 03e0d49d99
Optimize DFG partial assignments (#6176)
This is mostly a refactoring, but also enables handling some more
UNOPTFLAT, when the variable is only partially assigned in the cycle.

Previously the way partial assignments to variables were handled were
through the DfgVerexVar types themselves, which kept track of all
drivers. This has been replaced by DfgVertexSplice (which always drives
a DfgVeretexVar), and all DfgVertexVar now only have a single source,
either a DfgVertexSplice, if partially assigned, or an arbitrary
DfgVertex when updated as a whole.
2025-07-14 17:09:34 -04:00
Geza Lore 77180c4020
Optimize more cycles in DFG (#6173)
Added a second algorithm to break cycles in DFG by identifying which
bits of a circular variable are actually independent of the variable,
then reuse the existing (but extended) driver tracing algorithm to
eliminate them.

This can fix up things like: `assign gray = binary ^ (gray >> 1)`
2025-07-11 14:19:09 -04:00
Geza Lore ce77bac99a
Break some combinational cycles in DFG (#6168)
Added an algorithm that can break some combinational cycles in DFG, by
attempting to trace driver logic until we escape the cycle. This can
eliminate a decent portion of UNOPTFLAT warnings. E.g. due to this code:

```systemverilog
assign a[0] = .....;
assign a[1] = ~a[0];
```
2025-07-10 18:46:45 +01:00