4 Commits

Author	SHA1	Message	Date
Veripool API Bot	1f67080a1f	Tests: Verilog format	2026-03-09 21:39:16 -04:00
Wilson Snyder	7c6c6a684b	Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.	2026-01-26 20:24:34 -05:00
Wilson Snyder	078bb21a89	Add wire data type checking per IEEE.	2025-07-20 07:21:30 -04:00
Wilson Snyder	71dedccbbe	Support compile time trace signal selection with tracing_on/off (#3323).	2022-05-12 22:28:08 -04:00