Veripool API Bot
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1f67080a1f
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Tests: Verilog format
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2026-03-09 21:39:16 -04:00 |
Wilson Snyder
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7c6c6a684b
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Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
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2026-01-26 20:24:34 -05:00 |
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Wilson Snyder
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907047d823
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Tests: Remove unneeded AUTOARGS. No test change.
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2025-09-13 09:28:43 -04:00 |
Krzysztof Bieganski
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2f5c58b345
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Support `rand_mode` (#5273)
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
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2024-07-31 22:30:48 +01:00 |
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Wilson Snyder
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eff2d977c1
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Fix mis-elimination of variables across randomize()
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2023-11-12 07:32:08 -05:00 |
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Wilson Snyder
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99dbd23f1b
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Support passing constraints to --xml-only output (still otherwise unsupported) (#4683)
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2023-11-11 20:20:37 -05:00 |