luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
9,489 Commits 3 Branches 168 Tags 183 MiB
Commit Graph

2 Commits

Author SHA1 Message Date
Veripool API Bot 07ed6aef53 Tests: Verilog format 2026-03-08 18:26:40 -04:00
Wilson Snyder 214173c6b8 Support 1800-2023 preprocessor ifdef expressions; add PREPROC zero warning. 2024-03-02 10:15:19 -05:00