Veripool API Bot
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1f67080a1f
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Tests: Verilog format
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2026-03-09 21:39:16 -04:00 |
Wilson Snyder
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7c6c6a684b
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Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
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2026-01-26 20:24:34 -05:00 |
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Wilson Snyder
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1ce360ed5b
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Add SPDX license identifiers. No functional change.
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2020-03-21 11:24:24 -04:00 |
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Wilson Snyder
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bb20331f9e
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Fix signals in a concatenation on the LHS aren't created implicitly, bug206
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2010-01-19 19:35:05 -05:00 |
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Wilson Snyder
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52912c6329
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Convert repository to git from svn.
- Change .cvsignore to .gitignore
- Remove Id metacomments
- Cleanup whitespace at end of lines
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2008-06-09 21:25:10 -04:00 |
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Wilson Snyder
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ede37bb9d8
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Allow assigns to create implicit wires
git-svn-id: file://localhost/svn/verilator/trunk/verilator@1004 77ca24e4-aefa-0310-84f0-b9a241c72d87
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2008-03-20 01:40:22 +00:00 |