07ed6aef53
Tests: Verilog format
2026-03-08 18:26:40 -04:00
7c6c6a684b
Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
2026-01-26 20:24:34 -05:00
b820e1b587
Support `iff` in sensitivity list ( #1482 ) ( #4626 )
...
Adds a new field to `AstSenItem` that stores the `iff` condition which is then handled by `SenExprBuilder`.
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2023-11-29 19:10:32 +01:00
1f1d9312d2
Parse event 'iff', still unsupported.
2023-03-11 22:39:59 -05:00
3a5cbd5b67
Internals: Untabify some embedded tabs.
2021-11-13 10:46:25 -05:00
1ce360ed5b
Add SPDX license identifiers. No functional change.
2020-03-21 11:24:24 -04:00
ffa23b59b8
Tests: Add iff test, bug1482.
2019-07-26 19:31:02 -04:00
Veripool API Bot
Wilson Snyder
Krzysztof Bieganski