Veripool API Bot
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07ed6aef53
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Tests: Verilog format
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2026-03-08 18:26:40 -04:00 |
Wilson Snyder
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7c6c6a684b
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Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
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2026-01-26 20:24:34 -05:00 |
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Wilson Snyder
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2c156d6655
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Tests: Reformat some recent tests to mostly verilog-format standard. No test functional change.
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2025-12-20 21:46:43 -05:00 |
Geza Lore
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cf111d2e1f
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Do not create aliases for forced port signals (#5105)
+ don't remove forced signals in V3Const and Dfg
Fixes #5062
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2024-05-10 18:19:51 +01:00 |
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Wilson Snyder
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0c3ffa1841
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Support force/release (#2491) (#2593).
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2022-01-01 12:24:19 -05:00 |
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Wilson Snyder
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8952aa59ff
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Tests: Add force/release tests.
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2021-12-31 15:17:16 -05:00 |