Veripool API Bot
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07ed6aef53
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Tests: Verilog format
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2026-03-08 18:26:40 -04:00 |
AUDIY
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10eafb9b3f
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Add coverage type information to verilator_coverage annotation output (#7131) (#7133).
Fixes #7131.
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2026-02-24 20:59:42 -05:00 |
Wilson Snyder
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7c6c6a684b
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Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
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2026-01-26 20:24:34 -05:00 |
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Wilson Snyder
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68b227065e
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Tests: Fix coverage holes from t_dist_docs_options
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2025-10-25 11:00:25 -04:00 |
Ryszard Rozak
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95c8b7bb00
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Support separate coverage counters for toggles 0->1 and 1->0 (#6086)
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2025-08-20 07:31:04 -04:00 |
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Ryszard Rozak
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7d2b6bd921
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Internals: Optimize updates of Vtogcov signals. No functional change intended. (#6110)
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2025-08-04 13:29:56 +01:00 |
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Ryszard Rozak
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f9bdab65f0
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Fix coverage of variables of complex types (#6250)
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2025-08-01 13:24:18 +02:00 |
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Ryszard Rozak
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73b3648262
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Fix skipped genblocks in toggle coverage (#6010)
Signed-off-by: Ryszard Rozak <rrozak@antmicro.com>
Co-authored-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
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2025-05-16 08:24:57 -04:00 |
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Wilson Snyder
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11cfa61f80
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Fix casting etc of typedef'ed doubles.
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2025-05-04 16:34:37 -04:00 |
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Wilson Snyder
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7cc40d277b
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Tests: Cleanup some .out filenames. No test coverage change.
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2025-04-05 13:46:22 -04:00 |