4 Commits

Author	SHA1	Message	Date
Veripool API Bot	07ed6aef53	Tests: Verilog format	2026-03-08 18:26:40 -04:00
Wilson Snyder	7c6c6a684b	Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.	2026-01-26 20:24:34 -05:00
Pawel Kojma	37318ab2bd	Fix input sampling of clocking block signals (#6788)	2025-12-10 10:59:08 -05:00
Arkadiusz Kozdra	2cfec0ecc3	Support clocking blocks in virtual interfaces (#5235)	2024-07-09 18:31:58 -04:00