Veripool API Bot
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ce4d35aa85
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Verilog format
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2026-03-03 07:21:24 -05:00 |
Wilson Snyder
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7c6c6a684b
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Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
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2026-01-26 20:24:34 -05:00 |
Iztok Jeras
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2aa6a229ca
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Change range order warning from LITENDIAN to ASCRANGE (#4010)
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2023-03-20 20:44:11 -04:00 |
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Wilson Snyder
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1ce360ed5b
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Add SPDX license identifiers. No functional change.
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2020-03-21 11:24:24 -04:00 |
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Wilson Snyder
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8c9ca7a1b3
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Fix LITENDIAN warning on arrayed cells, bug1202.
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2017-09-13 19:09:49 -04:00 |
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Wilson Snyder
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9d055f8c13
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Fix ordering of arrayed cell wide connections, bug1202 partial.
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2017-09-12 19:34:10 -04:00 |