Commit Graph

2318 Commits

Author SHA1 Message Date
Wilson Snyder ebb37b0156 Merge branch 'master' into develop-v5 2022-08-20 14:02:09 -04:00
Wilson Snyder 90dc04cf93 Add --future0 and --future1 options. 2022-08-20 14:01:13 -04:00
Krzysztof Bieganski 10cf492946
Add support for expressions in event controls (#3550)
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-19 20:18:38 +02:00
Geza Lore 1404319b28 Merge branch 'master' into develop-v5 2022-08-19 13:39:44 +01:00
Ryszard Rozak db5fdfb0ee
Fix === with some tristate constants (#3551). 2022-08-18 07:03:05 -04:00
Wilson Snyder 93272c13fd Tests: Confirm fixed (#181) 2022-08-15 22:17:36 -04:00
Wilson Snyder 43abaeb055 Tests: Confirm fixed (#485) 2022-08-15 22:17:17 -04:00
Wilson Snyder 18b9e661c9 Tests: Confirm fixed (#446) 2022-08-15 22:17:09 -04:00
Wilson Snyder f435d96241 Fix case statement comparing string literal (#3544). 2022-08-15 21:56:09 -04:00
Mostafa Gamal df5f95a5bd
Fix nested default assignment for struct pattern (#3511) (#3524) 2022-08-12 06:55:07 -04:00
Drew Ranck b0c475205b
Fix void-cast queue pop_front or pop_back (#3542) (#3364)
Fix compile error for queue method usage, if it is the
first statement in a block of code, and the return
value is not used. Example:

>  if (foo)
>    void'(bar.pop_front());
2022-08-12 06:51:25 -04:00
Wilson Snyder cbe1b8e266 Fix segfault exporting non-existant package (#3535). 2022-08-08 17:53:50 -04:00
Yutetsu TAKATSUKASA d20f22beb1
Fix tristate logic when reading inout port in a module #3399 (#3523)
* Tests: Add a test to reproduce #3399

* Fix #3399. When reading an inout port in a module, it should refer the
original inout port, not the generated MODTEMP.
2022-08-07 21:12:57 +09:00
Wilson Snyder f4fe10844b Tests: Fix t_flag_help.pl (#3532). 2022-08-07 04:57:59 -04:00
Geza Lore c266739e9f Merge branch 'master' into develop-v5 2022-08-05 12:17:57 +01:00
Geza Lore 96a4b3e5a5 Update clang-format config and apply
- Regroup and sort #include directives (like we used to, but automatic)
- Set AlwaysBreakTemplateDeclarations to true
2022-08-05 12:00:24 +01:00
Geza Lore ad2fbfe62d Merge branch 'master' into develop-v5 2022-07-29 12:04:24 +01:00
Yutetsu TAKATSUKASA 1f9323d086
Set correct dtype in replaceShiftSame() (#3520)
* Tests: Add a test to reproduce bug3399

* Fix3399. Set the correct dtype in replaceShiftSame().

* Tests: update stats.

* Update Changes
2022-07-29 07:05:04 +09:00
Geza Lore 574dbfded1 V3MergeCond: Fix incorrect merge of assignments to the condition 2022-07-28 15:50:02 +01:00
github action e871cd8a44 Apply 'make format' 2022-07-25 21:47:29 +00:00
Mostafa Gamal 7b431b37c7
Fix struct pattern assignment (#2328) (#3517). 2022-07-25 17:46:22 -04:00
Gustav Svensk eeef5ab4de
Fix sformat string incorrectly cleared (#3515) (#3519). 2022-07-25 17:36:34 +02:00
Yutetsu TAKATSUKASA 60eab3eb8c
Fix wrong result of bit op tree optimization #3509 (#3516)
* Tests: Add a test to reproduce #3509

* Tests: Compile without tautological-compare check because bit op tree optimization is disabled in the test.

* Internals: Dedup code. No functional change is intended.

* Fix #3509.

"2'b10 == (2'b11 & {1'b0, val[0]})"  and "2'b10 != (2'b11 & {1'b0, val[0]})" were
wrongly optimized to "!val[0]" and "val[0]" respectively.
Now properly optimize them to 1'b0 and 1'b1.

* Commentary

* Commentary: Update Changes
2022-07-24 19:54:37 +09:00
Geza Lore 31abe537a0 Fix DPI export trigger sensitivity in 'nba'
Fixes #3508
2022-07-21 17:43:03 +01:00
Geza Lore f9ecbdc70b Merge branch 'master' into develop-v5 2022-07-21 09:56:14 +01:00
Geza Lore 30e3edb81d Remove deprecated and unused timescale override defines
These have been 'deprecated' for 2 years and are otherwise unused except
for using a temporary placeholder value, which I have inlined with the
default value.

Also remove the now VL_TIME_STR_CONVERT utility function (and
corresponding unit tests), which have no references in any project on
GitHub.
2022-07-20 14:06:09 +01:00
Arkadiusz Kozdra 542e324869
Wildcard index type support for associative arrays (#3501).
Associative arrays that specify a wildcard index type may be indexed by
integral expressions of any size, with leading zeros removed
automatically.  A natural representation for such expressions is a
string, especially that the standard explicitly specifies automatic
casts from string indices to bit vectors of equivalent size.
The automatic cast part is done implicitly by the existing type system.

A simpler way to just make this work would be to convert wildcard index
type to a string type directly in the parser code, but several new AST
classes are needed to make sure illegal method calls are detected.
The verilated data structure implementation is reused, because there is
no need for differentiating the behavior on C++ side.
2022-07-20 15:01:36 +02:00
Geza Lore db59c07f27 Implement trace offloading with fewer ifdefs
Step towards a proper run-time library. Reduce the amount of ifdefs in
the implementation of offloaded tracing. There are still a very small
number of ifdefs left, which will need more careful changes in order to
keep user API compatibility.
2022-07-19 11:31:35 +01:00
Geza Lore c28bf9ce24 Fix change detection over unpacked arrays. 2022-07-18 12:25:22 +01:00
Geza Lore 5a1f1796d7 Fix t/t_public_{clk,src}.pl after merge of master 2022-07-15 16:48:22 +01:00
Geza Lore ffc95fcf0e Merge branch 'master' into develop-v5 2022-07-15 16:48:14 +01:00
Todd Strader b0e796ca83
Public combo propagation issues (#2905) 2022-07-15 11:44:32 -04:00
Geza Lore 6a7bda6910 Correctly schedule combinational logic driven from DPI exports.
Fixes #3429.
2022-07-14 15:35:49 +01:00
Geza Lore c9ac9a75a6 Merge branch 'master' into develop-v5 2022-07-12 17:29:45 +01:00
Geza Lore f4038e3674
Move thread pool and execution profiler into the context. (#3477)
Fixes #3454
2022-07-12 11:41:15 +01:00
Arkadiusz Kozdra 8377514127
Add support for $test$plusargs(expr) (#3489) 2022-07-11 06:21:35 -04:00
Wilson Snyder d8ea989eda Tests/examples: Remove some legacy Verilator:: calls. 2022-07-09 09:50:50 -04:00
Wilson Snyder 5f3316d3dc * Fix empty string arguments to display (#3484). 2022-07-09 08:30:57 -04:00
Wilson Snyder a4fddb3fbe Fix table misoptimizing away display (#3488). 2022-07-09 07:55:46 -04:00
Yutetsu TAKATSUKASA 9f37cef1bb
Fix #3470 of incorrect bit op tree optimization (#3476)
* Tests: Add a test to reproduce #3470

* Update LSB during return path of traversal. No functional change is intended.

* Introduce LeafInfo::m_msb

* Update LeafInfo::m_msb when visitin AstCCast

* Internals: Add comment, reorder. No functional change is intended.

* Delete explicit from copy constructor to fix build error.

* Update Changes

* Internals: Remove unused parameter. No functional change is intended.

* Tests: Add explanation to t_const_opt.
2022-07-06 08:33:37 +09:00
Geza Lore 3aa8624658 Set 'threads' in tests via parameter to compile
This is in preparation to #3454.
2022-07-05 12:33:41 +01:00
Wilson Snyder b25b798dbe Merge branch 'master' into develop-v5 2022-07-04 13:20:03 -04:00
Geza Lore 383e384739 Remove always true cfg_with_threaded from test driver 2022-06-27 15:23:32 +01:00
Wilson Snyder e7ca4a69e3 Merge branch 'master' into develop-v5 2022-06-19 15:22:09 -04:00
Todd Strader 47b650d821
Fix public unpacked input ports (#3465) 2022-06-15 07:41:59 -04:00
Geza Lore 0c2c097377 Add -fno-merge-cond-motion option
This disables code motion during V3MergeCond, for debugging.
2022-06-13 14:16:11 +01:00
Kamil Rakoczy 660d1059b0
With --no-decoration, remove output whitespace (#3460)
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2022-06-10 07:26:33 -04:00
Wilson Snyder e7dc2de14b Fix BLKANDNBLK on $readmem/$writemem (#3379). 2022-06-04 12:43:18 -04:00
Wilson Snyder e2525d8440 Tests: Fix racy tests for develop-v5. 2022-06-04 12:22:11 -04:00
Wilson Snyder 6769106881 Merge branch 'master' into develop-v5 2022-06-04 12:17:29 -04:00
Wilson Snyder 32100a3c91 Tests: Fix racy tests for develop-v5. 2022-06-04 12:17:04 -04:00
Wilson Snyder 0f324c8309 Merge branch 'master' into develop-v5 2022-06-04 11:59:49 -04:00
Wilson Snyder 67f7432dd7 Commentary (#3436). 2022-06-04 08:37:42 -04:00
Wilson Snyder 59dc2853e3 Support concat assignment to packed array (#3446). 2022-06-03 21:32:13 -04:00
Wilson Snyder ada58465b2 Add -f<optimization> options to replace -O<letter> options (#3436). 2022-06-03 20:43:16 -04:00
Wilson Snyder 173f57c636 Changed --no-merge-const-pool to -fno-merge-const-pool (#3436). 2022-06-03 19:41:59 -04:00
Yutetsu TAKATSUKASA d64f979f99
Fix BitOpTree optimization to consider polarity of frozen node (#3445) (#3459)
* Tests: add a test to another failing case of #3445

* Consider polarity as lsb in BitOpTree optimization.
2022-06-01 09:26:16 +09:00
Yutetsu TAKATSUKASA 26b7452178
Fix #3445 of BitOpTreeOpt (#3453)
* Tests: Check BitOpTree statistics in t_const_opt.

* Tests: Add a test to reproduce #3445

* Fix #3445. Don't forget LSB of frozen node in BitOpTreeOpt.

* Apply suggestions from code review

Co-authored-by: Geza Lore <gezalore@gmail.com>
2022-05-30 19:33:06 +09:00
Geza Lore d45caca011 Remove legacy VCD tracing API
This has not been used by Verilator for a while, but was kept for
compatibility with some external code. Now removed.
2022-05-28 12:07:24 +01:00
Geza Lore 0722f47539
Improve V3MergeCond by reordering statements (#3125)
V3MergeCond merges consecutive conditional `_ = cond ? _ : _` and
`if (cond) ...` statements. This patch adds an analysis and ordering
phase that moves statements with identical conditions closer to each
other, in order to enable more merging opportunities. This in turn
eliminates a lot of repeated conditionals which reduced dynamic branch
count and branch misprediction rate. Observed 6.5% improvement on
multi-threaded large designs, at the cost of less than 2% increase in
Verilation speed.
2022-05-27 16:57:51 +01:00
Krzysztof Bieganski d7a75dc026 Merge branch 'master' into develop-v5 2022-05-25 11:06:38 +02:00
Wilson Snyder 530817191e Support non-ANSI interface port declarations (#3439). 2022-05-25 00:50:50 -04:00
Geza Lore 1282548a1c Only consider definitions in t_flag_csplit 2022-05-20 18:02:00 +01:00
Krzysztof Bieganski 9edccfdffa
Initial support for intra-assignment timing controls, net delays (#3427)
This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-05-17 19:19:44 +01:00
Geza Lore 1a056f6db9 Fix invalid conditional merging when starting at 'c = c ? a : b'
Fixes #3409.
2022-05-17 18:36:40 +01:00
Krzysztof Bieganski 0a91ddf38a
Tests: Better grep check in t_foreach (#3435)
This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-05-17 09:20:59 -04:00
Krzysztof Bieganski 67bb2c640e
Tests: Rename t_timing_clkgen to t_timing_clkgen1 (#3430)
This is a pre-PR to #3363, which will introduce more clock gen tests.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-05-17 09:19:51 -04:00
Geza Lore 282887d9c6 Fix code coverage holes
Fixes #3422
2022-05-16 21:22:21 +01:00
Krzysztof Bieganski ecaa07a72a
Rename AstTimingControl to AstEventControl (#3425)
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-05-16 20:44:41 +01:00
Wilson Snyder c3c46967dc Tests: Appease sanitizer (#3121). 2022-05-15 11:50:52 -04:00
Geza Lore 599d23697d
IEEE compliant scheduler (#3384)
This is a major re-design of the way code is scheduled in Verilator,
with the goal of properly supporting the Active and NBA regions of the
SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4.

With this change, all internally generated clocks should simulate
correctly, and there should be no more need for the `clock_enable` and
`clocker` attributes for correctness in the absence of Verilator
generated library models (`--lib-create`).

Details of the new scheduling model and algorithm are provided in
docs/internals.rst.

Implements #3278
2022-05-15 16:03:32 +01:00
Wilson Snyder 5aa12e9b51 Add assert when VerilatedContext is mis-deleted (#3121). 2022-05-15 10:51:03 -04:00
Wilson Snyder 3c4131d45d Fix 'with' operator with type casting (#3387). 2022-05-15 09:53:48 -04:00
Wilson Snyder ae8d8ee1ac Fix crash with misuse of display. 2022-05-15 09:29:45 -04:00
Geza Lore 766fb56651 Merge branch 'master' into develop-v5 2022-05-14 10:30:45 +01:00
Wilson Snyder 38438b3373 Internals: Cleanup some defaults. No functional change. 2022-05-12 23:30:39 -04:00
Wilson Snyder 71dedccbbe Support compile time trace signal selection with tracing_on/off (#3323). 2022-05-12 22:28:08 -04:00
Geza Lore bec4610e12 Merge branch 'master' into develop-v5 2022-05-08 15:50:50 +01:00
Kamil Rakoczy 9378259779
Fix UNOPTFLAT warning from initial static var (#3406)
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2022-05-06 10:24:03 +02:00
Wilson Snyder 3d762282b9 Fix hang with large case statement optimization (#3405). 2022-05-05 07:02:52 -04:00
Geza Lore 2ad0bcbba9 Merge branch 'master' into develop-v5 2022-05-01 16:49:42 +01:00
Wilson Snyder 915ceb2d04 Tests: Untabify tests. No functional change. 2022-05-01 10:10:00 -04:00
Geza Lore 88bb7cdca6 Merge branch 'master' into develop-v5 2022-04-29 17:14:11 +01:00
Geza Lore 49c90ecbce Issue consistent INITIALDLY/COMBDLY/BLKSEQ warnings
Some cases of warnings about the use of blocking and non-blocking
assignments in combinational vs sequential processes were suppressed in
a way that is inconsistent with the *actual* current execution model of
Verilator. Turning these back on to, well, warn the user that these might
cause unexpected results. V5 will clean these up, but until then err on
the side of caution.

Fixes #864.
2022-04-29 17:05:44 +01:00
Kamil Rakoczy 5de1c619c8
Fix foreach segmentation fault (#3400). 2022-04-28 06:11:31 -04:00
Yoda Lee a6d678d41d
Fix hang in generate symbol references (#3391) (#3398) 2022-04-27 18:40:36 -04:00
Geza Lore 46de9460a6 Merge branch 'master' into develop-v5 2022-04-23 15:38:30 +01:00
Geza Lore 62337bb6ac Future proofing some tests. No functional change. 2022-04-23 15:12:52 +01:00
Geza Lore 0b74e9b354 Ensure topological ordering of module list.
At the end of V3Param, fix up the module list to be topologically
sorted. We need to do this at the end as a later instantiation of a
recursive module might instantiate an earlier specialization, which we
cannot know until we processed everything. The rest of the compiler
depends on the module list being topologically sorted.

Fixes #3393
2022-04-23 13:25:27 +01:00
Geza Lore 5f0e1fae7f Simplify and clarify reporting of enclosing instance
Rename AstNodeModule::hierName -> someInstanceName and explain that this
is only used for user messages.

Rename AstNode::locationStr -> instanceStr and simplify implementation.
In particular, do not report an instance if we can't find a reasonable
guess.
2022-04-22 23:38:23 +01:00
Wilson Snyder 7bfc1a00a7 Fix tracing interfaces inside interfaces (#3309). 2022-04-14 09:14:44 -04:00
Wilson Snyder 92f64de115 Add FIXMEV5 comments 2022-04-13 22:18:59 -04:00
Geza Lore c79ea88576 Fix incorrect localization when encountering non-leaf functions.
Fixes #3286.
2022-04-09 20:30:39 +01:00
Wilson Snyder 33105f017c Commentary 2022-03-30 20:17:59 -04:00
Wilson Snyder e02f97854c Deprecate 'vluint64_t' and similar types (#3255). 2022-03-27 15:27:40 -04:00
Wilson Snyder 960d0de361 Tests: Cleanup vluint_t/vlsint_t in tests, part of (#3255) 2022-03-27 15:03:25 -04:00
Wilson Snyder 31ce1fdfd3 Tests: Check legacy part of (#3255) 2022-03-27 14:50:49 -04:00
Wilson Snyder 9821381059 Tests: new t_lint_latch_5 test (#2997). 2022-03-27 14:42:36 -04:00
Geza Lore b1b5b5dfe2 Improve run-time profiling
The --prof-threads option has been split into two independent options:
1. --prof-exec, for collecting verilator_gantt and other execution
related profiling data, and
2. --prof-pgo, for collecting data needed for PGO

The implementation of execution profiling is extricated from
VlThreadPool and is now a separate class VlExecutionProfiler. This means
--prof-exec can now be used for single-threaded models (though it does
not measure a lot of things just yet). For consistency VerilatedProfiler
is renamed VlPgoProfiler. Both VlExecutionProfiler and VlPgoProfiler are
in verilated_profiler.{h/cpp}, but can be used completely independently.

Also re-worked the execution profile format so it now only emits events
without holding onto any temporaries. This is in preparation for some
future optimizations that would be hindered by the introduction of function
locals via AstText.

Also removed the Barrier event. Clearing the profile buffers is not
notably more expensive as the profiling records are trivially
destructible.
2022-03-27 15:57:30 +02:00
Geza Lore c7440b250f Validate integer run-time arguments 2022-03-26 22:58:47 +00:00