luke/verilator
1
0
Fork 0
mirror of https://github.com/verilator/verilator.git synced 2026-10-06 10:03:44 +02:00
Code Issues Packages Projects Releases Wiki Activity
10,238 Commits 3 Branches 171 Tags
9da900a5e2b7dc5f0c70b26fdce348a2cbbffc5a
Commit Graph
8 Commits
Author SHA1 Message Date
Veripool API Bot 1f67080a1f Tests: Verilog format 2026-03-09 21:39:16 -04:00
Wilson Snyder 7c6c6a684b Add SPDX copyright identifiers, and get 'reuse' clean. No functional change. 2026-01-26 20:24:34 -05:00
Wilson Snyder 4a88ddc616 Tests: Fix interface syntax error 2024-11-09 17:22:16 -05:00
Wilson Snyder bbce7926b9 Tests: Remove unused clk input 2024-10-07 21:44:07 -04:00
Wilson Snyder b90b81e12c Tests: Fix string !== for other simulators. 2024-10-03 18:14:53 -04:00
Wilson Snyder d0e7eaafc9 Tests: Define stop uniformly. No functional change. 2024-02-08 18:39:13 -05:00
Wilson Snyder 1ce360ed5b Add SPDX license identifiers. No functional change. 2020-03-21 11:24:24 -04:00
Wilson Snyder 1471f5691a Fix error on multidimensional cells, bug1505. 2019-09-12 19:06:26 -04:00