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5 Commits
Author SHA1 Message Date
Veripool API Bot 1f67080a1f Tests: Verilog format 2026-03-09 21:39:16 -04:00
Wilson Snyder 7c6c6a684b Add SPDX copyright identifiers, and get 'reuse' clean. No functional change. 2026-01-26 20:24:34 -05:00
Wilson Snyder 29ed866061 Fix range inheritance on port without data type (#2753). 2021-03-11 19:22:19 -05:00
Wilson Snyder e88dff6929 Tests: Improve t_mod_interface_array4 2021-03-11 13:32:38 -05:00
Wilson Snyder fd6edd90bc Fix little endian interface pin swizzling (#2475). 2021-02-20 22:11:20 -05:00