4 Commits

Author	SHA1	Message	Date
Veripool API Bot	07ed6aef53	Tests: Verilog format	2026-03-08 18:26:40 -04:00
Ryszard Rozak	af2327aaf4	Fix hierarchical references with parameterized modules and interfaces (#5649) (#6566)	2025-10-17 09:06:46 -04:00
Wilson Snyder	e9fe8f65a8	Change error messages to more often suggest documentation	2025-04-05 17:10:44 -04:00
Wilson Snyder	5021989cb6	Tests: Rename interface-to-wire (#5649 test partial)	2024-11-30 19:05:26 -05:00