07ed6aef53
Tests: Verilog format
2026-03-08 18:26:40 -04:00
7c6c6a684b
Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
2026-01-26 20:24:34 -05:00
907047d823
Tests: Remove unneeded AUTOARGS. No test change.
2025-09-13 09:28:43 -04:00
078bb21a89
Add wire data type checking per IEEE.
2025-07-20 07:21:30 -04:00
679a4314dc
Tests: Avoid side effect on array index
2023-09-01 19:26:50 -04:00
d80e0523cc
Fix nonsensical permissions of some files in test_regress/t ( #3912 )
...
chmod a-x *.out *.v *.vlt
2023-01-29 20:32:19 -05:00
e7068369fe
Fix $display of fixed-width numbers ( #3565 ).
2022-10-18 21:10:35 -04:00
c207e98306
Implement a distinct constant pool ( #3013 )
...
What previously used to be per module static constants created in
V3Table and V3Prelim are now merged globally within the whole model and
emitted as part of a separate constant pool. Members of the constant
pool are global variables which are declared lazily when used (similar to
loose methods).
2021-06-13 15:05:55 +01:00
f6c0108c86
Optimize large lookup tables to static data ( #2926 )
...
Implements #2925
2021-05-08 20:04:56 +01:00
Veripool API Bot
Wilson Snyder
Larry Doolittle
Geza Lore