3 Commits

Author	SHA1	Message	Date
Veripool API Bot	07ed6aef53	Tests: Verilog format	2026-03-08 18:26:40 -04:00
Wilson Snyder	7c6c6a684b	Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.	2026-01-26 20:24:34 -05:00
Geza Lore	25f5db4b5f	DFG: Allow inlining of variabels driven from forced vars (#5259) ... Not sure why this was disabled before, but it seems legal to me to change 'forced A' -> 'B' -> 'C' into 'forced A' -> 'B', 'forced A' -> 'C' Fixes #5249	2024-07-13 12:35:09 +01:00