verilator

Commit Graph

Author	SHA1	Message	Date
Veripool API Bot	ce4d35aa85	Verilog format	2026-03-03 07:21:24 -05:00
Wilson Snyder	7c6c6a684b	Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.	2026-01-26 20:24:34 -05:00
Geza Lore	599d23697d	IEEE compliant scheduler (#3384 ) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278	2022-05-15 16:03:32 +01:00

Author

SHA1

Message

Date

Veripool API Bot

ce4d35aa85

Verilog format

2026-03-03 07:21:24 -05:00

Wilson Snyder

7c6c6a684b

Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.

2026-01-26 20:24:34 -05:00

Geza Lore

599d23697d

IEEE compliant scheduler (#3384 )

This is a major re-design of the way code is scheduled in Verilator,
with the goal of properly supporting the Active and NBA regions of the
SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4.

With this change, all internally generated clocks should simulate
correctly, and there should be no more need for the `clock_enable` and
`clocker` attributes for correctness in the absence of Verilator
generated library models (`--lib-create`).

Details of the new scheduling model and algorithm are provided in
docs/internals.rst.

Implements #3278

2022-05-15 16:03:32 +01:00

3 Commits