Artur Bieniek
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87bebbb732
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Support global $assertcontrol (#7807)
Signed-off-by: Artur Bieniek <abieniek@antmicro.com>
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2026-06-22 18:51:41 -04:00 |
Veripool API Bot
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ce4d35aa85
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Verilog format
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2026-03-03 07:21:24 -05:00 |
Wilson Snyder
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7c6c6a684b
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Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
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2026-01-26 20:24:34 -05:00 |
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Wilson Snyder
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50a5a1ff5b
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Tests: Fix some verilog.y parser coverage holes
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2024-07-26 07:29:15 -04:00 |
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Wilson Snyder
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915ceb2d04
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Tests: Untabify tests. No functional change.
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2022-05-01 10:10:00 -04:00 |
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Wilson Snyder
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1ce360ed5b
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Add SPDX license identifiers. No functional change.
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2020-03-21 11:24:24 -04:00 |
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Wilson Snyder
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097107bd0b
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Support 'assume' similar to 'assert', bug1269.
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2018-01-31 07:33:10 -05:00 |
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Wilson Snyder
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87b9cb49ad
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Fix / multi-argument ordering, bug816.
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2014-09-04 22:25:19 -04:00 |
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Wilson Snyder
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c41dfcf6ad
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Fix assertions broken from bug725, bug743.
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2014-04-16 22:33:25 -04:00 |
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Wilson Snyder
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52912c6329
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Convert repository to git from svn.
- Change .cvsignore to .gitignore
- Remove Id metacomments
- Cleanup whitespace at end of lines
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2008-06-09 21:25:10 -04:00 |
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Wilson Snyder
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79ab50d84f
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Support trivial SV assertions
git-svn-id: file://localhost/svn/verilator/trunk/verilator@898 77ca24e4-aefa-0310-84f0-b9a241c72d87
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2007-03-06 21:43:38 +00:00 |