luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
8,569 Commits 2 Branches 166 Tags 162 MiB
Commit Graph

2 Commits

Author SHA1 Message Date
Wilson Snyder 6e8bd3da19 Internals/Tests: Cleanup some missing dev coverage items 2025-10-11 12:54:55 -04:00
Geza Lore d330100542 Create implicit nets for inputs of gate primitives. 
Prior to this we failed to create implicit nets for inputs of gate
primitives, which is required by the standard (IEEE 1800-2017 6.10).
Note: outputs were covered due to being modeled as the LHS of
assignments, which do create implicit nets.
 2023-10-21 22:45:26 +01:00