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verilator
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9,730 Commits 3 Branches 169 Tags 199 MiB
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4 Commits

Author SHA1 Message Date
Wilson Snyder 1653b982b9 Verilog format 2026-05-13 21:00:34 -04:00
Wilson Snyder 7c6c6a684b Add SPDX copyright identifiers, and get 'reuse' clean. No functional change. 2026-01-26 20:24:34 -05:00
Wilson Snyder 915ceb2d04 Tests: Untabify tests. No functional change. 2022-05-01 10:10:00 -04:00
Wilson Snyder 748fa4cb80 Fix coredump after huge enum warning. 2021-12-10 23:08:03 -05:00