9 Commits

Include renames

Author	SHA1	Message	Date
Veripool API Bot	07ed6aef53	Tests: Verilog format	2026-03-08 18:26:40 -04:00
Wilson Snyder	7c6c6a684b	Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.	2026-01-26 20:24:34 -05:00
Geza Lore	a8dca71ed0	Support more complex combinational assignments in DFG. (#6205) ... Previously DFG was limited to having a Sel, or an ArraySel potentially under a Concat on the LHS of combinational assignments. Other forms or combinations were not representable in the graph. This adds support for arbitrary combinations of the above by combining DfgSplicePacked and DfgSpliceArray vertices introduced in #6176. In particular, Sel(ArraySel(VarRef,_),_) enables a lot more code to be represented in DFG.	2025-07-21 12:33:12 -04:00
Wilson Snyder	915ceb2d04	Tests: Untabify tests. No functional change.	2022-05-01 10:10:00 -04:00
Wilson Snyder	3a5cbd5b67	Internals: Untabify some embedded tabs.	2021-11-13 10:46:25 -05:00
Wilson Snyder	1ce360ed5b	Add SPDX license identifiers. No functional change.	2020-03-21 11:24:24 -04:00
Wilson Snyder	c28a6eef3b	Fix whitespace issues, bug1203.	2017-09-11 19:18:58 -04:00
Wilson Snyder	6e6f1045b8	Fix per-bit array output connection error, bug414.	2013-02-02 18:33:10 -05:00
Wilson Snyder	e4c96d5be5	Fix array of instantiations with sub-range output, bug414.	2011-11-28 22:10:43 -05:00