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mirror of https://github.com/verilator/verilator.git synced 2026-09-04 00:30:34 +02:00
Code Issues Packages Projects Releases Wiki Activity
9,643 Commits 2 Branches 170 Tags
2ebb99aaa2687c55cd9ee2e4e584eb5379db1221
Commit Graph
9 Commits
Author SHA1 Message Date
Veripool API Bot ce4d35aa85 Verilog format 2026-03-03 07:21:24 -05:00
Wilson Snyder 7c6c6a684b Add SPDX copyright identifiers, and get 'reuse' clean. No functional change. 2026-01-26 20:24:34 -05:00
Iztok Jeras 2aa6a229ca Change range order warning from LITENDIAN to ASCRANGE (#4010) 2023-03-20 20:44:11 -04:00
Wilson Snyder 915ceb2d04 Tests: Untabify tests. No functional change. 2022-05-01 10:10:00 -04:00
Wilson Snyder 1ce360ed5b Add SPDX license identifiers. No functional change. 2020-03-21 11:24:24 -04:00
Wilson Snyder 45702e319b Support $size/$bits/etc on type references. 2017-11-23 10:17:56 -05:00
Wilson Snyder c28a6eef3b Fix whitespace issues, bug1203. 2017-09-11 19:18:58 -04:00
Wilson Snyder 91e2d1d2a0 Tests: Make struct test pass. 2013-01-17 22:45:35 -05:00
Wilson Snyder 6949f35f22 Tests: Add t_array_query, t_sv_conditional, bug473 2012-04-12 18:15:39 -04:00
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