verilator

Commit Graph

Author	SHA1	Message	Date
Geza Lore	745605efe3	Fix DFG removing forceable signals (#4942 ) DFG could remove forceable signals by replacing them with their in-design driver. This is a bit of a pain to prevent, and ideally the forcing transform should happen before DFG, but implementing it there is a pain due to having to rewrite ports based on direction. This is an attempted fix in DFG. More cases might remain.	2024-03-03 16:22:41 +00:00
Geza Lore	f8c0169e82	Implement 'forceable' attribute Using the 'forceable' directive in a configuration file, or the /* verilator forceable */ metacomment on a variable declaration will generate additional public signals that allow the specified signals to be forced/released from the C++ code.	2022-01-16 15:31:37 +00:00

Author

SHA1

Message

Date

Geza Lore

745605efe3

Fix DFG removing forceable signals (#4942 )

DFG could remove forceable signals by replacing them with their
in-design driver. This is a bit of a pain to prevent, and ideally the
forcing transform should happen before DFG, but implementing it there is
a pain due to having to rewrite ports based on direction.  This is an
attempted fix in DFG. More cases might remain.

2024-03-03 16:22:41 +00:00

Geza Lore

f8c0169e82

Implement 'forceable' attribute

Using the 'forceable' directive in a configuration file, or the /*
verilator forceable */ metacomment on a variable declaration will
generate additional public signals that allow the specified signals to
be forced/released from the C++ code.

2022-01-16 15:31:37 +00:00

2 Commits