Wilson Snyder
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1653b982b9
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Verilog format
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2026-05-13 21:00:34 -04:00 |
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Wilson Snyder
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e238a2ca5e
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Verilog format
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2026-02-22 13:50:01 -05:00 |
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Wilson Snyder
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7c6c6a684b
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Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
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2026-01-26 20:24:34 -05:00 |
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Wilson Snyder
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44102de362
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Tests: Rename control files to .vc. No test function change.
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2025-11-22 12:09:22 -05:00 |
Bartłomiej Chmiel
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32f9cf072b
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Fix hierarchical verilation for projects with dot-f dependency lists (#5199) (#5669)
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2024-12-12 11:25:19 -05:00 |