luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Tests: Make t_lint_syncasyncnet_bad etc tolerate -Oi.

This commit is contained in:
Wilson Snyder 2020-11-25 21:42:47 -05:00
parent 380137a402
commit ffbae97a3d
3 changed files with 16 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
test_regress/t/t_lint_syncasyncnet_bad.out
View File

@ -1,9 +1,9 @@
%Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:16:25: Signal flopped as both synchronous and async: 'rst_both_l' %Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:14:10: Signal flopped as both synchronous and async: 'rst_both_l'
t/t_lint_syncasyncnet_bad.v:91:15: ... Location of async usage t/t_lint_syncasyncnet_bad.v:52:15: ... Location of async usage
91 | q2 <= (~rst_both_l) ? 1'b0 : d; 52 | q4 <= (~rst_both_l) ? 1'b0 : d;
| ^~~~~~~~~~ | ^~~~~~~~~~
t/t_lint_syncasyncnet_bad.v:59:14: ... Location of sync usage t/t_lint_syncasyncnet_bad.v:34:14: ... Location of sync usage
59 | q2 <= (rst_both_l) ? d : 1'b0; 34 | q2 <= (rst_both_l) ? d : 1'b0;
| ^~~~~~~~~~ | ^~~~~~~~~~
... Use "/* verilator lint_off SYNCASYNCNET */" and lint_on around source to disable this message. ... Use "/* verilator lint_off SYNCASYNCNET */" and lint_on around source to disable this message.
%Error: Exiting due to %Error: Exiting due to

58
test_regress/t/t_lint_syncasyncnet_bad.v
View File

@ -6,40 +6,15 @@
module t (/*AUTOARG*/ module t (/*AUTOARG*/
// Inputs // Inputs
rst_sync_l, rst_both_l, rst_async_l, d, clk clk, rst_both_l, rst_sync_l, rst_async_l, d
); );
/*AUTOINPUT*/ /*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clk; // To sub1 of sub1.v, ...
input d; // To sub1 of sub1.v, ...
input rst_async_l; // To sub2 of sub2.v
input rst_both_l; // To sub1 of sub1.v, ...
input rst_sync_l; // To sub1 of sub1.v
// End of automatics
sub1 sub1 (/*AUTOINST*/
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_sync_l (rst_sync_l),
.d (d));
sub2 sub2 (/*AUTOINST*/
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_async_l (rst_async_l),
.d (d));
endmodule
module sub1 (/*AUTOARG*/
// Inputs
clk, rst_both_l, rst_sync_l, d
);
input clk; input clk;
input rst_both_l; input rst_both_l;
input rst_sync_l; input rst_sync_l;
//input rst_async_l; input rst_async_l;
input d; input d;
reg q1; reg q1;
reg q2; reg q2;
@ -60,40 +35,27 @@ module sub1 (/*AUTOARG*/
if (0 && q1 && q2) ; if (0 && q1 && q2) ;
end end
endmodule
module sub2 (/*AUTOARG*/
// Inputs
clk, rst_both_l, rst_async_l, d
);
input clk;
input rst_both_l;
//input rst_sync_l;
input rst_async_l;
input d;
reg q1;
reg q2;
reg q3; reg q3;
always @(posedge clk or negedge rst_async_l) begin always @(posedge clk or negedge rst_async_l) begin
if (~rst_async_l) begin if (~rst_async_l) begin
/*AUTORESET*/ /*AUTORESET*/
// Beginning of autoreset for uninitialized flops // Beginning of autoreset for uninitialized flops
q1 <= 1'h0; q3 <= 1'h0;
// End of automatics // End of automatics
end else begin end else begin
q1 <= d; q3 <= d;
end end
end end
reg q4;
always @(posedge clk or negedge rst_both_l) begin always @(posedge clk or negedge rst_both_l) begin
q2 <= (~rst_both_l) ? 1'b0 : d; q4 <= (~rst_both_l) ? 1'b0 : d;
end end
// Make there be more async uses than sync uses // Make there be more async uses than sync uses
reg q5;
always @(posedge clk or negedge rst_both_l) begin always @(posedge clk or negedge rst_both_l) begin
q3 <= (~rst_both_l) ? 1'b0 : d; q5 <= (~rst_both_l) ? 1'b0 : d;
if (0 && q1 && q2 && q3) ; if (0 && q3 && q4 && q5) ;
end end
endmodule endmodule

2
test_regress/t/t_mem_twoedge.v
View File

@ -90,9 +90,9 @@ module Test (/*AUTOARG*/
input [7:0] d0; input [7:0] d0;
input [7:0] d1; input [7:0] d1;
output reg [31:0] out; output reg [31:0] out;
// verilator lint_off MULTIDRIVEN
output reg [15:0] out2; output reg [15:0] out2;
// verilator lint_off MULTIDRIVEN
reg [7:0] mem [4]; reg [7:0] mem [4];
// verilator lint_on MULTIDRIVEN // verilator lint_on MULTIDRIVEN