From ffbae97a3d2bf553f673645a82b34284e559abc9 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 25 Nov 2020 21:42:47 -0500 Subject: [PATCH] Tests: Make t_lint_syncasyncnet_bad etc tolerate -Oi. --- test_regress/t/t_lint_syncasyncnet_bad.out | 10 ++-- test_regress/t/t_lint_syncasyncnet_bad.v | 58 ++++------------------ test_regress/t/t_mem_twoedge.v | 2 +- 3 files changed, 16 insertions(+), 54 deletions(-) diff --git a/test_regress/t/t_lint_syncasyncnet_bad.out b/test_regress/t/t_lint_syncasyncnet_bad.out index fd13ef2e0..dd4ca5627 100644 --- a/test_regress/t/t_lint_syncasyncnet_bad.out +++ b/test_regress/t/t_lint_syncasyncnet_bad.out @@ -1,9 +1,9 @@ -%Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:16:25: Signal flopped as both synchronous and async: 'rst_both_l' - t/t_lint_syncasyncnet_bad.v:91:15: ... Location of async usage - 91 | q2 <= (~rst_both_l) ? 1'b0 : d; +%Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:14:10: Signal flopped as both synchronous and async: 'rst_both_l' + t/t_lint_syncasyncnet_bad.v:52:15: ... Location of async usage + 52 | q4 <= (~rst_both_l) ? 1'b0 : d; | ^~~~~~~~~~ - t/t_lint_syncasyncnet_bad.v:59:14: ... Location of sync usage - 59 | q2 <= (rst_both_l) ? d : 1'b0; + t/t_lint_syncasyncnet_bad.v:34:14: ... Location of sync usage + 34 | q2 <= (rst_both_l) ? d : 1'b0; | ^~~~~~~~~~ ... Use "/* verilator lint_off SYNCASYNCNET */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_syncasyncnet_bad.v b/test_regress/t/t_lint_syncasyncnet_bad.v index f941d0514..9db96f3fe 100644 --- a/test_regress/t/t_lint_syncasyncnet_bad.v +++ b/test_regress/t/t_lint_syncasyncnet_bad.v @@ -6,40 +6,15 @@ module t (/*AUTOARG*/ // Inputs - rst_sync_l, rst_both_l, rst_async_l, d, clk + clk, rst_both_l, rst_sync_l, rst_async_l, d ); /*AUTOINPUT*/ - // Beginning of automatic inputs (from unused autoinst inputs) - input clk; // To sub1 of sub1.v, ... - input d; // To sub1 of sub1.v, ... - input rst_async_l; // To sub2 of sub2.v - input rst_both_l; // To sub1 of sub1.v, ... - input rst_sync_l; // To sub1 of sub1.v - // End of automatics - - sub1 sub1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .rst_both_l (rst_both_l), - .rst_sync_l (rst_sync_l), - .d (d)); - sub2 sub2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .rst_both_l (rst_both_l), - .rst_async_l (rst_async_l), - .d (d)); -endmodule - -module sub1 (/*AUTOARG*/ - // Inputs - clk, rst_both_l, rst_sync_l, d - ); input clk; input rst_both_l; input rst_sync_l; - //input rst_async_l; + input rst_async_l; + input d; reg q1; reg q2; @@ -60,40 +35,27 @@ module sub1 (/*AUTOARG*/ if (0 && q1 && q2) ; end -endmodule - -module sub2 (/*AUTOARG*/ - // Inputs - clk, rst_both_l, rst_async_l, d - ); - - input clk; - input rst_both_l; - //input rst_sync_l; - input rst_async_l; - input d; - reg q1; - reg q2; reg q3; - always @(posedge clk or negedge rst_async_l) begin if (~rst_async_l) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops - q1 <= 1'h0; + q3 <= 1'h0; // End of automatics end else begin - q1 <= d; + q3 <= d; end end + reg q4; always @(posedge clk or negedge rst_both_l) begin - q2 <= (~rst_both_l) ? 1'b0 : d; + q4 <= (~rst_both_l) ? 1'b0 : d; end // Make there be more async uses than sync uses + reg q5; always @(posedge clk or negedge rst_both_l) begin - q3 <= (~rst_both_l) ? 1'b0 : d; - if (0 && q1 && q2 && q3) ; + q5 <= (~rst_both_l) ? 1'b0 : d; + if (0 && q3 && q4 && q5) ; end endmodule diff --git a/test_regress/t/t_mem_twoedge.v b/test_regress/t/t_mem_twoedge.v index 2a2af9faf..9c241853c 100644 --- a/test_regress/t/t_mem_twoedge.v +++ b/test_regress/t/t_mem_twoedge.v @@ -90,9 +90,9 @@ module Test (/*AUTOARG*/ input [7:0] d0; input [7:0] d1; output reg [31:0] out; + // verilator lint_off MULTIDRIVEN output reg [15:0] out2; - // verilator lint_off MULTIDRIVEN reg [7:0] mem [4]; // verilator lint_on MULTIDRIVEN