Fix randcase under fork (#6843).

This commit is contained in:
Wilson Snyder 2025-12-20 21:25:01 -05:00
parent f990dd747e
commit ffa87540cc
4 changed files with 44 additions and 0 deletions

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@ -111,6 +111,7 @@ Verilator 5.043 devel
* Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande] * Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande]
* Fix duplicate name error with interface initial blocks (#6804) (#6805). [Thomas Dybdahl Ahle] * Fix duplicate name error with interface initial blocks (#6804) (#6805). [Thomas Dybdahl Ahle]
* Fix firing array selects of events (#6829). [Amal Araweelo Almis] * Fix firing array selects of events (#6829). [Amal Araweelo Almis]
* Fix randcase under fork (#6843). [Amal Araweelo Almis]
Verilator 5.042 2025-11-02 Verilator 5.042 2025-11-02

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@ -2634,6 +2634,7 @@ class RandomizeVisitor final : public VNVisitor {
const std::string name = "__Vrandcase" + cvtToStr(m_randCaseNum++); const std::string name = "__Vrandcase" + cvtToStr(m_randCaseNum++);
AstVar* const randVarp = new AstVar{fl, VVarType::BLOCKTEMP, name, sumDTypep}; AstVar* const randVarp = new AstVar{fl, VVarType::BLOCKTEMP, name, sumDTypep};
randVarp->noSubst(true); randVarp->noSubst(true);
randVarp->lifetime(VLifetime::AUTOMATIC_EXPLICIT);
if (m_ftaskp) randVarp->funcLocal(true); if (m_ftaskp) randVarp->funcLocal(true);
AstNodeExpr* sump = new AstConst{fl, AstConst::WidthedValue{}, 64, 0}; AstNodeExpr* sump = new AstConst{fl, AstConst::WidthedValue{}, 64, 0};
AstNodeIf* const firstIfsp AstNodeIf* const firstIfsp

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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator_st')
test.compile(verilator_flags2=['--binary'])
test.execute()
test.passes()

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@ -0,0 +1,24 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module randcase_tb;
int count;
initial begin
for (int i = 0; i < 100; i++) begin
fork
randcase
1: count++;
5: count--;
3: ;
endcase
join_none
end
#1;
if (count > 30) $stop; // Realistically won't happen (10^25) though not impossible
$write("*-* All Finished *-*\n");
$finish;
end
endmodule