Fix power operator calculation, bug730.
This commit is contained in:
Wilson Snyder
parent
b6913ff9b3
commit
ff19dd94f9
2
Changes
2
Changes
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@ -25,6 +25,8 @@ indicates the contributor was also the author of the fix; Thanks!
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**** Fix modport function import not-found error.
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**** Fix power operator calculation, bug730. [Clifford Wolf]
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**** Fix Mac OS-X test issues. [Holger Waechtler]
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**** Fix C++-2011 warnings.
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@ -1163,7 +1163,10 @@ static inline WDataOutP VL_MODDIVS_WWW(int lbits, WDataOutP owp,WDataInP lwp,WDa
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}
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}
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#define VL_POW_QQI(obits,lbits,rbits,lhs,rhs) VL_POW_QQQ(obits,lbits,rbits,lhs,rhs)
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static inline IData VL_POW_III(int, int, int rbits, IData lhs, IData rhs) {
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if (VL_UNLIKELY(rhs==0)) return 1;
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if (VL_UNLIKELY(lhs==0)) return 0;
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IData power = lhs;
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IData out = 1;
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@ -1173,10 +1176,8 @@ static inline IData VL_POW_III(int, int, int rbits, IData lhs, IData rhs) {
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}
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return out;
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}
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#define VL_POW_QQI(obits,lbits,rbits,lhs,rhs) VL_POW_QQQ(obits,lbits,rbits,lhs,rhs)
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static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) {
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if (VL_UNLIKELY(rhs==0)) return 1;
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if (VL_UNLIKELY(lhs==0)) return 0;
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QData power = lhs;
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QData out = VL_ULL(1);
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@ -1187,6 +1188,36 @@ static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) {
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return out;
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}
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#define VL_POWSS_QQI(obits,lbits,rbits,lhs,rhs,lsign,rsign) VL_POWSS_QQQ(obits,lbits,rbits,lhs,rhs,lsign,rsign)
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static inline IData VL_POWSS_III(int obits, int, int rbits, IData lhs, IData rhs, bool lsign, bool rsign) {
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if (VL_UNLIKELY(rhs==0)) return 1;
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if (rsign && VL_SIGN_I(rbits, rhs)) {
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if (lhs==0) return 0; // "X"
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else if (lhs==1) return 1;
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else if (lsign && lhs==VL_MASK_I(obits)) { //-1
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if (rhs & 1) return VL_MASK_I(obits); // -1^odd=-1
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else return 1; // -1^even=1
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}
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return 0;
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}
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return VL_POW_III(obits, obits, rbits, lhs, rhs);
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}
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static inline QData VL_POWSS_QQQ(int obits, int, int rbits, QData lhs, QData rhs, bool lsign, bool rsign) {
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if (VL_UNLIKELY(rhs==0)) return 1;
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if (rsign && VL_SIGN_I(rbits, rhs)) {
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if (lhs==0) return 0; // "X"
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else if (lhs==1) return 1;
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else if (lsign && lhs==VL_MASK_I(obits)) { //-1
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if (rhs & 1) return VL_MASK_I(obits); // -1^odd=-1
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else return 1; // -1^even=1
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}
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return 0;
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}
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return VL_POW_QQQ(obits, obits, rbits, lhs, rhs);
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}
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//===================================================================
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// Concat/replication
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@ -4036,7 +4036,7 @@ struct AstPow : public AstNodeBiop {
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virtual bool cleanOut() {return false;}
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virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
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virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return false;}
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virtual int instrCount() const { return widthInstrs()*instrCountMul(); }
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virtual int instrCount() const { return widthInstrs()*instrCountMul()*10; }
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};
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struct AstPowD : public AstNodeBiop {
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AstPowD(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
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@ -4048,20 +4048,46 @@ struct AstPowD : public AstNodeBiop {
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virtual bool cleanOut() {return false;}
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virtual bool cleanLhs() {return false;} virtual bool cleanRhs() {return false;}
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virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
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virtual int instrCount() const { return instrCountDoubleDiv(); }
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virtual int instrCount() const { return instrCountDoubleDiv()*5; }
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virtual bool doubleFlavor() const { return true; }
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};
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struct AstPowS : public AstNodeBiop {
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AstPowS(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
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struct AstPowSU : public AstNodeBiop {
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AstPowSU(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
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dtypeFrom(lhsp); }
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ASTNODE_NODE_FUNCS(PowS, POWS)
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virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opPowS(lhs,rhs); }
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ASTNODE_NODE_FUNCS(PowSU, POWSU)
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virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opPowSU(lhs,rhs); }
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virtual string emitVerilog() { return "%k(%l %f** %r)"; }
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virtual string emitC() { return "VL_POWS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
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virtual string emitC() { return "VL_POWSS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri, 1,0)"; }
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virtual bool cleanOut() {return false;}
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virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
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virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return false;}
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virtual int instrCount() const { return widthInstrs()*instrCountMul(); }
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virtual int instrCount() const { return widthInstrs()*instrCountMul()*10; }
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virtual bool signedFlavor() const { return true; }
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};
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struct AstPowSS : public AstNodeBiop {
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AstPowSS(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
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dtypeFrom(lhsp); }
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ASTNODE_NODE_FUNCS(PowSS, POWSS)
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virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opPowSS(lhs,rhs); }
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virtual string emitVerilog() { return "%k(%l %f** %r)"; }
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virtual string emitC() { return "VL_POWSS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri, 1,1)"; }
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virtual bool cleanOut() {return false;}
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virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
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virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return false;}
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virtual int instrCount() const { return widthInstrs()*instrCountMul()*10; }
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virtual bool signedFlavor() const { return true; }
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};
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struct AstPowUS : public AstNodeBiop {
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AstPowUS(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
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dtypeFrom(lhsp); }
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ASTNODE_NODE_FUNCS(PowUS, POWUS)
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virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opPowUS(lhs,rhs); }
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virtual string emitVerilog() { return "%k(%l %f** %r)"; }
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virtual string emitC() { return "VL_POWSS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri, 0,1)"; }
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virtual bool cleanOut() {return false;}
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virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
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virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return false;}
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virtual int instrCount() const { return widthInstrs()*instrCountMul()*10; }
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virtual bool signedFlavor() const { return true; }
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};
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struct AstEqCase : public AstNodeBiCom {
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@ -1794,8 +1794,14 @@ private:
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TREEOP ("AstDivS {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)");
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TREEOP ("AstMul {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)");
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TREEOP ("AstMulS {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)");
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TREEOP ("AstPow {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)");
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TREEOP ("AstPowS {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)");
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TREEOP ("AstPow {$rhsp.isZero}", "replaceNum(nodep, 1)"); // Overrides lhs zero rule
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TREEOP ("AstPowSS {$rhsp.isZero}", "replaceNum(nodep, 1)"); // Overrides lhs zero rule
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TREEOP ("AstPowSU {$rhsp.isZero}", "replaceNum(nodep, 1)"); // Overrides lhs zero rule
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TREEOP ("AstPowUS {$rhsp.isZero}", "replaceNum(nodep, 1)"); // Overrides lhs zero rule
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TREEOP ("AstPow {$lhsp.isZero, !$rhsp.isZero}", "replaceZeroChkPure(nodep,$rhsp)");
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TREEOP ("AstPowSU {$lhsp.isZero, !$rhsp.isZero}", "replaceZeroChkPure(nodep,$rhsp)");
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TREEOP ("AstPowUS {$lhsp.isZero, !$rhsp.isZero}", "replaceZeroChkPure(nodep,$rhsp)");
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TREEOP ("AstPowSU {$lhsp.isZero, !$rhsp.isZero}", "replaceZeroChkPure(nodep,$rhsp)");
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TREEOP ("AstOr {$lhsp.isZero, $rhsp}", "replaceWRhs(nodep)");
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TREEOP ("AstShiftL{$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)");
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TREEOP ("AstShiftR{$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)");
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@ -1834,7 +1840,6 @@ private:
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TREEOP ("AstMul {operandIsPowTwo($lhsp), $rhsp}", "replaceMulShift(nodep)"); // a*2^n -> a<<n
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TREEOP ("AstDiv {$lhsp, operandIsPowTwo($rhsp)}", "replaceDivShift(nodep)"); // a/2^n -> a>>n
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TREEOP ("AstPow {operandIsTwo($lhsp), $rhsp}", "replacePowShift(nodep)"); // 2**a == 1<<a
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TREEOP ("AstPowS {operandIsTwo($lhsp), $rhsp}", "replacePowShift(nodep)"); // 2**a == 1<<a
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// Trinary ops
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// Note V3Case::Sel requires Cond to always be conditionally executed in C to prevent core dump!
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TREEOP ("AstNodeCond{$condp.isZero, $expr1p, $expr2p}", "replaceWChild(nodep,$expr2p)");
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@ -1073,9 +1073,13 @@ void EmitCStmts::emitOpName(AstNode* nodep, const string& format,
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break;
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}
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}
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} else if (pos[0] == ')') {
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nextComma=""; puts(")");
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} else if (pos[0] == '(') {
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COMMA; needComma = false; puts("(");
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} else {
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// Normal text
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if (pos[0] == ')') nextComma="";
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if (isalnum(pos[0])) needComma = true;
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COMMA;
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string s; s+=pos[0]; puts(s);
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}
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@ -1381,13 +1381,23 @@ V3Number& V3Number::opModDivGuts(const V3Number& lhs, const V3Number& rhs, bool
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}
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}
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V3Number& V3Number::opPow (const V3Number& lhs, const V3Number& rhs) {
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V3Number& V3Number::opPow (const V3Number& lhs, const V3Number& rhs, bool lsign, bool rsign) {
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// L(i) bit return, if any 4-state, 4-state return
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if (lhs.isFourState() || rhs.isFourState()) return setAllBitsX();
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if (lhs.isEqZero()) return setZero();
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if (rhs.isEqZero()) return setQuad(1); // Overrides lhs 0 -> return 0
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// We may want to special case when the lhs is 2, so we can get larger outputs
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if (lhs.width()>64) m_fileline->v3fatalSrc("Unsupported: Large >64bit ** math not implemented yet: "<<*this);
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if (rhs.width()>64) m_fileline->v3fatalSrc("Unsupported: Large >64bit ** math not implemented yet: "<<*this);
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if (rsign && rhs.isNegative()) {
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if (lhs.isEqZero()) return setAllBitsX();
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else if (lhs.isEqOne()) return setQuad(1);
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else if (lsign && lhs.isEqAllOnes()) {
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if (rhs.bitIs1(0)) return setAllBits1(); // -1^odd=-1
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else return setQuad(1); // -1^even=1
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}
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return setZero();
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}
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if (lhs.isEqZero()) return setZero();
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setZero();
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m_value[0] = 1;
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V3Number power (lhs.m_fileline, width()); power.opAssign(lhs);
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@ -1404,14 +1414,14 @@ V3Number& V3Number::opPow (const V3Number& lhs, const V3Number& rhs) {
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}
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return *this;
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}
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V3Number& V3Number::opPowS (const V3Number& lhs, const V3Number& rhs) {
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// Signed multiply
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if (lhs.isFourState() || rhs.isFourState()) return setAllBitsX();
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if (lhs.isEqZero() && rhs.isNegative()) return setAllBitsX(); // Per spec
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if (!lhs.isNegative() && !rhs.isNegative()) return opPow(lhs,rhs);
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//if (lhs.isNegative() || rhs.isNonIntegral()) return setAllBitsX(); // Illegal pow() call
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m_fileline->v3fatalSrc("Unsupported: Power (**) operator with negative numbers: "<<*this);
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return setAllBitsX();
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V3Number& V3Number::opPowSU (const V3Number& lhs, const V3Number& rhs) {
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return opPow(lhs,rhs,true,false);
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}
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V3Number& V3Number::opPowSS (const V3Number& lhs, const V3Number& rhs) {
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return opPow(lhs,rhs,true,true);
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}
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V3Number& V3Number::opPowUS (const V3Number& lhs, const V3Number& rhs) {
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return opPow(lhs,rhs,false,true);
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}
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V3Number& V3Number::opBufIf1 (const V3Number& ens, const V3Number& if1s) {
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@ -238,8 +238,10 @@ public:
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V3Number& opDivS (const V3Number& lhs, const V3Number& rhs); // Signed
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V3Number& opModDiv (const V3Number& lhs, const V3Number& rhs);
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V3Number& opModDivS (const V3Number& lhs, const V3Number& rhs); // Signed
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V3Number& opPow (const V3Number& lhs, const V3Number& rhs);
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V3Number& opPowS (const V3Number& lhs, const V3Number& rhs); // Signed
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V3Number& opPow (const V3Number& lhs, const V3Number& rhs, bool lsign=false, bool rsign=false);
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V3Number& opPowSU (const V3Number& lhs, const V3Number& rhs); // Signed lhs, unsigned rhs
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V3Number& opPowSS (const V3Number& lhs, const V3Number& rhs); // Signed lhs, signed rhs
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V3Number& opPowUS (const V3Number& lhs, const V3Number& rhs); // Unsigned lhs, signed rhs
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V3Number& opAnd (const V3Number& lhs, const V3Number& rhs);
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V3Number& opChangeXor(const V3Number& lhs, const V3Number& rhs);
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V3Number& opXor (const V3Number& lhs, const V3Number& rhs);
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@ -614,7 +614,7 @@ private:
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}
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}
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virtual void visit(AstPow* nodep, AstNUser* vup) {
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// Pow is special, output sign only depends on LHS sign
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// Pow is special, output sign only depends on LHS sign, but function result depends on both signs
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// Real if either side is real (as with AstAdd)
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shift_prelim(nodep, vup);
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if (nodep->lhsp()->isDouble() || nodep->rhsp()->isDouble()) {
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@ -622,21 +622,46 @@ private:
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spliceCvtD(nodep->rhsp());
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replaceWithDVersion(nodep); nodep=NULL;
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} else {
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AstNodeBiop* newp = shift_final(nodep, vup); nodep=NULL;
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newp->dtypeChgSigned(newp->lhsp()->isSigned());
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if (newp->isSigned()) {
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replaceWithUOrSVersion(newp, false); newp=NULL;
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if (vup->c()->final()) {
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int width=nodep->width(); int ewidth=nodep->widthMin();
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nodep->lhsp()->iterateAndNext(*this,WidthVP(width,ewidth,FINAL).p());
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// rhs already finalized in shift_prelim
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widthCheck(nodep,"LHS",nodep->lhsp(),width,ewidth);
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nodep->dtypeChgSigned(nodep->lhsp()->isSigned());
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AstNode* newp = NULL; // No change
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if (nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned()) {
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newp = new AstPowSS (nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
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nodep->rhsp()->unlinkFrBack());
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} else if (nodep->lhsp()->isSigned() && !nodep->rhsp()->isSigned()) {
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newp = new AstPowSU (nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
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nodep->rhsp()->unlinkFrBack());
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} else if (!nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned()) {
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newp = new AstPowUS (nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
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nodep->rhsp()->unlinkFrBack());
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}
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if (newp) {
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newp->dtypeFrom(nodep);
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UINFO(9,"powOld "<<nodep<<endl);
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UINFO(9,"powNew "<<newp<<endl);
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nodep->replaceWith(newp); nodep=NULL;
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}
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}
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}
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}
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virtual void visit(AstPowS* nodep, AstNUser* vup) {
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// Pow is special, output sign only depends on LHS sign
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shift_prelim(nodep, vup);
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AstNodeBiop* newp = shift_final(nodep, vup); nodep=NULL;
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newp->dtypeChgSigned(newp->lhsp()->isSigned());
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if (!newp->isSigned()) {
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replaceWithUOrSVersion(newp, true); newp=NULL;
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}
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virtual void visit(AstPowSU* nodep, AstNUser* vup) {
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// POWSU/SS/US only created here, dtype already determined, so nothing to do in this function
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nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
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nodep->rhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
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}
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virtual void visit(AstPowSS* nodep, AstNUser* vup) {
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// POWSU/SS/US only created here, dtype already determined, so nothing to do in this function
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nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
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nodep->rhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
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}
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virtual void visit(AstPowUS* nodep, AstNUser* vup) {
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// POWSU/SS/US only created here, dtype already determined, so nothing to do in this function
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nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
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nodep->rhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
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}
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virtual void visit(AstCountOnes* nodep, AstNUser* vup) {
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if (vup->c()->prelim()) {
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|
|
@ -2533,8 +2558,6 @@ private:
|
|||
case AstType::atMODDIVS: newp = new AstModDiv (fl,lhsp,rhsp); break;
|
||||
case AstType::atMUL: newp = new AstMulS (fl,lhsp,rhsp); break;
|
||||
case AstType::atMULS: newp = new AstMul (fl,lhsp,rhsp); break;
|
||||
case AstType::atPOW: newp = new AstPowS (fl,lhsp,rhsp); break;
|
||||
case AstType::atPOWS: newp = new AstPow (fl,lhsp,rhsp); break;
|
||||
case AstType::atSHIFTR: newp = new AstShiftRS (fl,lhsp,rhsp); break;
|
||||
case AstType::atSHIFTRS: newp = new AstShiftR (fl,lhsp,rhsp); break;
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -3,6 +3,12 @@
|
|||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2005 by Wilson Snyder.
|
||||
|
||||
`ifdef VERILATOR
|
||||
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
|
||||
`else
|
||||
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
|
||||
`endif
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
|
|
@ -28,11 +34,13 @@ module t (/*AUTOARG*/
|
|||
$write("%0x %x %x\n", cyc, p, shifted);
|
||||
`endif
|
||||
// Constant versions
|
||||
if (61'h1 ** 21'h31 != 61'h1) $stop;
|
||||
if (61'h2 ** 21'h10 != 61'h10000) $stop;
|
||||
if (61'd10 ** 21'h3 != 61'h3e8) $stop;
|
||||
if (61'h3 ** 21'h7 != 61'h88b) $stop;
|
||||
if (61'h7ab3811219 ** 21'ha6e30 != 61'h01ea58c703687e81) $stop;
|
||||
`checkh(61'h1 ** 21'h31, 61'h1);
|
||||
`checkh(61'h2 ** 21'h10, 61'h10000);
|
||||
`checkh(61'd10 ** 21'h3, 61'h3e8);
|
||||
`checkh(61'h3 ** 21'h7, 61'h88b);
|
||||
`ifndef VCS
|
||||
`checkh(61'h7ab3811219 ** 21'ha6e30, 61'h01ea58c703687e81);
|
||||
`endif
|
||||
if (cyc==1) begin
|
||||
a <= 61'h0;
|
||||
b <= 21'h0;
|
||||
|
|
@ -71,25 +79,25 @@ module t (/*AUTOARG*/
|
|||
32'd01: ;
|
||||
32'd02: ; // 0^x is indeterminate
|
||||
32'd03: ; // 0^x is indeterminate
|
||||
32'd04: if (p!=61'h1) $stop;
|
||||
32'd05: if (p!=61'h10000) $stop;
|
||||
32'd06: if (p!=61'h3e8) $stop;
|
||||
32'd07: if (p!=61'h88b) $stop;
|
||||
32'd08: if (p!=61'h01ea58c703687e81) $stop;
|
||||
32'd09: if (p!=61'h01ea58c703687e81) $stop;
|
||||
32'd04: `checkh(p, 61'h1);
|
||||
32'd05: `checkh(p, 61'h10000);
|
||||
32'd06: `checkh(p, 61'h3e8);
|
||||
32'd07: `checkh(p, 61'h88b);
|
||||
32'd08: `checkh(p, 61'h01ea58c703687e81);
|
||||
32'd09: `checkh(p, 61'h01ea58c703687e81);
|
||||
default: $stop;
|
||||
endcase
|
||||
case (cyc)
|
||||
32'd00: ;
|
||||
32'd01: ;
|
||||
32'd02: if (shifted!=61'h0000000000000001) $stop;
|
||||
32'd03: if (shifted!=61'h0000000000000008) $stop;
|
||||
32'd04: if (shifted!=61'h0002000000000000) $stop;
|
||||
32'd05: if (shifted!=61'h0000000000010000) $stop;
|
||||
32'd06: if (shifted!=61'h0000000000000008) $stop;
|
||||
32'd07: if (shifted!=61'h0000000000000080) $stop;
|
||||
32'd08: if (shifted!=61'h0000000000000000) $stop;
|
||||
32'd09: if (shifted!=61'h0000000000000000) $stop;
|
||||
32'd02: `checkh(shifted, 61'h0000000000000001);
|
||||
32'd03: `checkh(shifted, 61'h0000000000000008);
|
||||
32'd04: `checkh(shifted, 61'h0002000000000000);
|
||||
32'd05: `checkh(shifted, 61'h0000000000010000);
|
||||
32'd06: `checkh(shifted, 61'h0000000000000008);
|
||||
32'd07: `checkh(shifted, 61'h0000000000000080);
|
||||
32'd08: `checkh(shifted, 61'h0000000000000000);
|
||||
32'd09: `checkh(shifted, 61'h0000000000000000);
|
||||
default: $stop;
|
||||
endcase
|
||||
end
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
#!/usr/bin/perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
|
||||
compile (
|
||||
);
|
||||
|
||||
execute (
|
||||
check_finished=>1,
|
||||
);
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2014 by Wilson Snyder.
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
//wire [31:0] pow32b = {24'h0,crc[15:8]}**crc[7:0]; // Overflows
|
||||
wire [3:0] pow4b = crc[7:4]**crc[3:0];
|
||||
wire [63:0] result = {60'h0, pow4b};
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
// What checksum will we end up with (above print should match)
|
||||
`define EXPECTED_SUM 64'h1fec4b2b71cf8024
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
#!/usr/bin/perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
|
||||
compile (
|
||||
);
|
||||
|
||||
execute (
|
||||
check_finished=>1,
|
||||
);
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2004 by Wilson Snyder.
|
||||
|
||||
`ifdef VERILATOR
|
||||
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
|
||||
`else
|
||||
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
|
||||
`endif
|
||||
|
||||
module t (/*AUTOARG*/);
|
||||
|
||||
// IEEE says for ** the size is L(i). Thus Icarus Verilog is wrong in sizing some of the below.
|
||||
|
||||
initial begin
|
||||
// NC=67b6cfc1b29a21 VCS=c1b29a20(wrong) IV=67b6cfc1b29a21 Verilator=67b6cfc1b29a21
|
||||
$display("15 ** 14 = %0x expect 67b6cfc1b29a21", 64'b1111 ** 64'b1110);
|
||||
// NC=1 VCS=0 IV=0 Verilator=1 (wrong,fixed)
|
||||
$display("15 **-4'sd2 = %0x expect 0 (per IEEE negative power)", ((-4'd1 ** -4'sd2)));
|
||||
// NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1
|
||||
$display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((-4'd1 ** -4'd2)));
|
||||
// NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1
|
||||
$display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((4'd15 ** 4'd14)));
|
||||
// NC=8765432187654321 VCS=8765432187654000(wrong) IV=8765432187654321 Verilator=8765432187654321
|
||||
$display("64'big ** 1 = %0x expect %0x", 64'h8765432187654321 ** 1, 64'h8765432187654321);
|
||||
$display("\n");
|
||||
|
||||
`checkh( (64'b1111 ** 64'b1110), 64'h67b6cfc1b29a21);
|
||||
`checkh( (-4'd1 ** -4'sd2), 4'h0); //bug730
|
||||
`checkh( (-4'd1 ** -4'd2), 4'h1);
|
||||
`checkh( (4'd15 ** 4'd14), 4'h1);
|
||||
`checkh( (64'h8765432187654321 ** 4'h1), 64'h8765432187654321);
|
||||
|
||||
`checkh((-8'sh3 ** 8'h3) , 8'he5 ); // a**b (-27)
|
||||
`checkh((-8'sh1 ** 8'h2) , 8'h1 ); // -1^odd=-1, -1^even=1
|
||||
`checkh((-8'sh1 ** 8'h3) , 8'hff ); // -1^odd=-1, -1^even=1
|
||||
`checkh(( 8'h0 ** 8'h3) , 8'h0 ); // 0
|
||||
`checkh(( 8'h1 ** 8'h3) , 8'h1 ); // 1
|
||||
`checkh(( 8'h3 ** 8'h3) , 8'h1b ); // a**b (27)
|
||||
`checkh(( 8'sh3 ** 8'h3) , 8'h1b ); // a**b (27)
|
||||
`checkh(( 8'h6 ** 8'h3) , 8'hd8 ); // a**b (216)
|
||||
`checkh(( 8'sh6 ** 8'h3) , 8'hd8 ); // a**b (216)
|
||||
|
||||
`checkh((-8'sh3 ** 8'sh3), 8'he5 ); // a**b
|
||||
`checkh((-8'sh1 ** 8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1
|
||||
`checkh((-8'sh1 ** 8'sh3), 8'hff ); // -1^odd=-1, -1^even=1
|
||||
`checkh(( 8'h0 ** 8'sh3), 8'h0 ); // 0
|
||||
`checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1
|
||||
`checkh(( 8'h3 ** 8'sh3), 8'h1b ); // a**b (27)
|
||||
`checkh(( 8'sh3 ** 8'sh3), 8'h1b ); // a**b (27)
|
||||
`checkh(( 8'h6 ** 8'sh3), 8'hd8 ); // a**b (216)
|
||||
`checkh(( 8'sh6 ** 8'sh3), 8'hd8 ); // a**b (216)
|
||||
|
||||
`checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
|
||||
`checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
|
||||
`checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
|
||||
`checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1
|
||||
`checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1
|
||||
`checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1
|
||||
`checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
|
||||
|
||||
`checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
|
||||
`checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
|
||||
`checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
|
||||
`checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1
|
||||
`checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1
|
||||
`checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1
|
||||
`checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
|
||||
|
||||
`checkh((-8'sh3 ** -8'sh3), 8'h0 ); // 0 (a<-1) // NCVERILOG bug
|
||||
`checkh((-8'sh1 ** -8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1
|
||||
`checkh((-8'sh1 ** -8'sh3), 8'hff); // -1^odd=-1, -1^even=1
|
||||
// `checkh(( 8'h0 ** -8'sh3), 8'hx ); // x // NCVERILOG bug
|
||||
`checkh(( 8'h1 ** -8'sh3), 8'h1 ); // 1**b always 1
|
||||
`checkh(( 8'h3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug
|
||||
`checkh(( 8'sh3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug
|
||||
|
||||
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -7,6 +7,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
|
|||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
|
||||
!$Self->{vcs} or $Self->unsupported("VCS does ** wrong");
|
||||
|
||||
compile (
|
||||
);
|
||||
|
||||
|
|
|
|||
|
|
@ -48,11 +48,7 @@ module t (/*AUTOARG*/
|
|||
// Do a few in each group
|
||||
wire [1:0] o1 = ~ a; // Can't get more than one reduction to parse
|
||||
wire [1:0] o2 = ^ b; // Can't get more than one reduction to parse
|
||||
`ifdef verilator
|
||||
wire [1:0] o3 = a ** b ** c;
|
||||
`else // A commercial simulator gets this wrong, so calc manually
|
||||
wire [1:0] o3 = pow(pow(a,b),c);
|
||||
`endif
|
||||
wire [1:0] o3 = a ** b ** c; // Some simulators botch this
|
||||
|
||||
wire [1:0] o4 = a * b / cnz % dnz * enz;
|
||||
wire [1:0] o5 = a + b - c + d;
|
||||
|
|
@ -68,13 +64,8 @@ module t (/*AUTOARG*/
|
|||
wire [1:0] o15 = a ? b : c ? d : e;
|
||||
|
||||
// Now cross each pair of groups
|
||||
`ifdef verilator
|
||||
wire [1:0] x1 = ~ a ** ~ b ** ~c;
|
||||
wire [1:0] x2 = a ** b * c ** d;
|
||||
`else
|
||||
wire [1:0] x1 = pow(pow(~ a, ~ b), ~c);
|
||||
wire [1:0] x2 = pow(a,b) * pow(c,d);
|
||||
`endif
|
||||
wire [1:0] x1 = ~ a ** ~ b ** ~c; // Some simulators botch this
|
||||
wire [1:0] x2 = a ** b * c ** d; // Some simulators botch this
|
||||
wire [1:0] x3 = a + b * c + d;
|
||||
wire [1:0] x4 = a + b << c + d;
|
||||
wire [1:0] x5 = a == b << c == d;
|
||||
|
|
@ -160,7 +151,7 @@ module t (/*AUTOARG*/
|
|||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
// What checksum will we end up with (above print should match)
|
||||
`define EXPECTED_SUM 64'h34b4e0b25bb03880
|
||||
`define EXPECTED_SUM 64'h2756ea365ec7520e
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
|
|
|
|||
Loading…
Reference in New Issue