From ff19dd94f939f6cba29595a266e7465b6b4d4653 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 5 Apr 2014 15:44:49 -0400 Subject: [PATCH] Fix power operator calculation, bug730. --- Changes | 2 + include/verilated.h | 37 +++++++++++-- src/V3AstNodes.h | 42 ++++++++++++--- src/V3Const.cpp | 11 ++-- src/V3EmitC.cpp | 6 ++- src/V3Number.cpp | 30 +++++++---- src/V3Number.h | 6 ++- src/V3Width.cpp | 53 ++++++++++++------ test_regress/t/t_math_pow.v | 46 +++++++++------- test_regress/t/t_math_pow2.pl | 18 +++++++ test_regress/t/t_math_pow2.v | 50 +++++++++++++++++ test_regress/t/t_math_pow3.pl | 18 +++++++ test_regress/t/t_math_pow3.v | 83 +++++++++++++++++++++++++++++ test_regress/t/t_math_precedence.pl | 2 + test_regress/t/t_math_precedence.v | 17 ++---- 15 files changed, 347 insertions(+), 74 deletions(-) create mode 100755 test_regress/t/t_math_pow2.pl create mode 100644 test_regress/t/t_math_pow2.v create mode 100755 test_regress/t/t_math_pow3.pl create mode 100644 test_regress/t/t_math_pow3.v diff --git a/Changes b/Changes index 19fd02a32..20ced9b36 100644 --- a/Changes +++ b/Changes @@ -25,6 +25,8 @@ indicates the contributor was also the author of the fix; Thanks! **** Fix modport function import not-found error. +**** Fix power operator calculation, bug730. [Clifford Wolf] + **** Fix Mac OS-X test issues. [Holger Waechtler] **** Fix C++-2011 warnings. diff --git a/include/verilated.h b/include/verilated.h index 364a8994f..f0afc4273 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -1163,7 +1163,10 @@ static inline WDataOutP VL_MODDIVS_WWW(int lbits, WDataOutP owp,WDataInP lwp,WDa } } +#define VL_POW_QQI(obits,lbits,rbits,lhs,rhs) VL_POW_QQQ(obits,lbits,rbits,lhs,rhs) + static inline IData VL_POW_III(int, int, int rbits, IData lhs, IData rhs) { + if (VL_UNLIKELY(rhs==0)) return 1; if (VL_UNLIKELY(lhs==0)) return 0; IData power = lhs; IData out = 1; @@ -1173,10 +1176,8 @@ static inline IData VL_POW_III(int, int, int rbits, IData lhs, IData rhs) { } return out; } - -#define VL_POW_QQI(obits,lbits,rbits,lhs,rhs) VL_POW_QQQ(obits,lbits,rbits,lhs,rhs) - static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) { + if (VL_UNLIKELY(rhs==0)) return 1; if (VL_UNLIKELY(lhs==0)) return 0; QData power = lhs; QData out = VL_ULL(1); @@ -1187,6 +1188,36 @@ static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) { return out; } +#define VL_POWSS_QQI(obits,lbits,rbits,lhs,rhs,lsign,rsign) VL_POWSS_QQQ(obits,lbits,rbits,lhs,rhs,lsign,rsign) + +static inline IData VL_POWSS_III(int obits, int, int rbits, IData lhs, IData rhs, bool lsign, bool rsign) { + if (VL_UNLIKELY(rhs==0)) return 1; + if (rsign && VL_SIGN_I(rbits, rhs)) { + if (lhs==0) return 0; // "X" + else if (lhs==1) return 1; + else if (lsign && lhs==VL_MASK_I(obits)) { //-1 + if (rhs & 1) return VL_MASK_I(obits); // -1^odd=-1 + else return 1; // -1^even=1 + } + return 0; + } + return VL_POW_III(obits, obits, rbits, lhs, rhs); +} + +static inline QData VL_POWSS_QQQ(int obits, int, int rbits, QData lhs, QData rhs, bool lsign, bool rsign) { + if (VL_UNLIKELY(rhs==0)) return 1; + if (rsign && VL_SIGN_I(rbits, rhs)) { + if (lhs==0) return 0; // "X" + else if (lhs==1) return 1; + else if (lsign && lhs==VL_MASK_I(obits)) { //-1 + if (rhs & 1) return VL_MASK_I(obits); // -1^odd=-1 + else return 1; // -1^even=1 + } + return 0; + } + return VL_POW_QQQ(obits, obits, rbits, lhs, rhs); +} + //=================================================================== // Concat/replication diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index d580801a2..e755972b5 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -4036,7 +4036,7 @@ struct AstPow : public AstNodeBiop { virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;} virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return false;} - virtual int instrCount() const { return widthInstrs()*instrCountMul(); } + virtual int instrCount() const { return widthInstrs()*instrCountMul()*10; } }; struct AstPowD : public AstNodeBiop { AstPowD(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) { @@ -4048,20 +4048,46 @@ struct AstPowD : public AstNodeBiop { virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return false;} virtual bool cleanRhs() {return false;} virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;} - virtual int instrCount() const { return instrCountDoubleDiv(); } + virtual int instrCount() const { return instrCountDoubleDiv()*5; } virtual bool doubleFlavor() const { return true; } }; -struct AstPowS : public AstNodeBiop { - AstPowS(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) { +struct AstPowSU : public AstNodeBiop { + AstPowSU(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) { dtypeFrom(lhsp); } - ASTNODE_NODE_FUNCS(PowS, POWS) - virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opPowS(lhs,rhs); } + ASTNODE_NODE_FUNCS(PowSU, POWSU) + virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opPowSU(lhs,rhs); } virtual string emitVerilog() { return "%k(%l %f** %r)"; } - virtual string emitC() { return "VL_POWS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } + virtual string emitC() { return "VL_POWSS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri, 1,0)"; } virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;} virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return false;} - virtual int instrCount() const { return widthInstrs()*instrCountMul(); } + virtual int instrCount() const { return widthInstrs()*instrCountMul()*10; } + virtual bool signedFlavor() const { return true; } +}; +struct AstPowSS : public AstNodeBiop { + AstPowSS(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) { + dtypeFrom(lhsp); } + ASTNODE_NODE_FUNCS(PowSS, POWSS) + virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opPowSS(lhs,rhs); } + virtual string emitVerilog() { return "%k(%l %f** %r)"; } + virtual string emitC() { return "VL_POWSS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri, 1,1)"; } + virtual bool cleanOut() {return false;} + virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;} + virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return false;} + virtual int instrCount() const { return widthInstrs()*instrCountMul()*10; } + virtual bool signedFlavor() const { return true; } +}; +struct AstPowUS : public AstNodeBiop { + AstPowUS(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) { + dtypeFrom(lhsp); } + ASTNODE_NODE_FUNCS(PowUS, POWUS) + virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opPowUS(lhs,rhs); } + virtual string emitVerilog() { return "%k(%l %f** %r)"; } + virtual string emitC() { return "VL_POWSS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri, 0,1)"; } + virtual bool cleanOut() {return false;} + virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;} + virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return false;} + virtual int instrCount() const { return widthInstrs()*instrCountMul()*10; } virtual bool signedFlavor() const { return true; } }; struct AstEqCase : public AstNodeBiCom { diff --git a/src/V3Const.cpp b/src/V3Const.cpp index 9f24227b4..bc4e541ff 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -1794,8 +1794,14 @@ private: TREEOP ("AstDivS {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)"); TREEOP ("AstMul {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)"); TREEOP ("AstMulS {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)"); - TREEOP ("AstPow {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)"); - TREEOP ("AstPowS {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)"); + TREEOP ("AstPow {$rhsp.isZero}", "replaceNum(nodep, 1)"); // Overrides lhs zero rule + TREEOP ("AstPowSS {$rhsp.isZero}", "replaceNum(nodep, 1)"); // Overrides lhs zero rule + TREEOP ("AstPowSU {$rhsp.isZero}", "replaceNum(nodep, 1)"); // Overrides lhs zero rule + TREEOP ("AstPowUS {$rhsp.isZero}", "replaceNum(nodep, 1)"); // Overrides lhs zero rule + TREEOP ("AstPow {$lhsp.isZero, !$rhsp.isZero}", "replaceZeroChkPure(nodep,$rhsp)"); + TREEOP ("AstPowSU {$lhsp.isZero, !$rhsp.isZero}", "replaceZeroChkPure(nodep,$rhsp)"); + TREEOP ("AstPowUS {$lhsp.isZero, !$rhsp.isZero}", "replaceZeroChkPure(nodep,$rhsp)"); + TREEOP ("AstPowSU {$lhsp.isZero, !$rhsp.isZero}", "replaceZeroChkPure(nodep,$rhsp)"); TREEOP ("AstOr {$lhsp.isZero, $rhsp}", "replaceWRhs(nodep)"); TREEOP ("AstShiftL{$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)"); TREEOP ("AstShiftR{$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)"); @@ -1834,7 +1840,6 @@ private: TREEOP ("AstMul {operandIsPowTwo($lhsp), $rhsp}", "replaceMulShift(nodep)"); // a*2^n -> a< a>>n TREEOP ("AstPow {operandIsTwo($lhsp), $rhsp}", "replacePowShift(nodep)"); // 2**a == 1< return 0 // We may want to special case when the lhs is 2, so we can get larger outputs if (lhs.width()>64) m_fileline->v3fatalSrc("Unsupported: Large >64bit ** math not implemented yet: "<<*this); if (rhs.width()>64) m_fileline->v3fatalSrc("Unsupported: Large >64bit ** math not implemented yet: "<<*this); + if (rsign && rhs.isNegative()) { + if (lhs.isEqZero()) return setAllBitsX(); + else if (lhs.isEqOne()) return setQuad(1); + else if (lsign && lhs.isEqAllOnes()) { + if (rhs.bitIs1(0)) return setAllBits1(); // -1^odd=-1 + else return setQuad(1); // -1^even=1 + } + return setZero(); + } + if (lhs.isEqZero()) return setZero(); setZero(); m_value[0] = 1; V3Number power (lhs.m_fileline, width()); power.opAssign(lhs); @@ -1404,14 +1414,14 @@ V3Number& V3Number::opPow (const V3Number& lhs, const V3Number& rhs) { } return *this; } -V3Number& V3Number::opPowS (const V3Number& lhs, const V3Number& rhs) { - // Signed multiply - if (lhs.isFourState() || rhs.isFourState()) return setAllBitsX(); - if (lhs.isEqZero() && rhs.isNegative()) return setAllBitsX(); // Per spec - if (!lhs.isNegative() && !rhs.isNegative()) return opPow(lhs,rhs); - //if (lhs.isNegative() || rhs.isNonIntegral()) return setAllBitsX(); // Illegal pow() call - m_fileline->v3fatalSrc("Unsupported: Power (**) operator with negative numbers: "<<*this); - return setAllBitsX(); +V3Number& V3Number::opPowSU (const V3Number& lhs, const V3Number& rhs) { + return opPow(lhs,rhs,true,false); +} +V3Number& V3Number::opPowSS (const V3Number& lhs, const V3Number& rhs) { + return opPow(lhs,rhs,true,true); +} +V3Number& V3Number::opPowUS (const V3Number& lhs, const V3Number& rhs) { + return opPow(lhs,rhs,false,true); } V3Number& V3Number::opBufIf1 (const V3Number& ens, const V3Number& if1s) { diff --git a/src/V3Number.h b/src/V3Number.h index 610a151bc..eade3f973 100644 --- a/src/V3Number.h +++ b/src/V3Number.h @@ -238,8 +238,10 @@ public: V3Number& opDivS (const V3Number& lhs, const V3Number& rhs); // Signed V3Number& opModDiv (const V3Number& lhs, const V3Number& rhs); V3Number& opModDivS (const V3Number& lhs, const V3Number& rhs); // Signed - V3Number& opPow (const V3Number& lhs, const V3Number& rhs); - V3Number& opPowS (const V3Number& lhs, const V3Number& rhs); // Signed + V3Number& opPow (const V3Number& lhs, const V3Number& rhs, bool lsign=false, bool rsign=false); + V3Number& opPowSU (const V3Number& lhs, const V3Number& rhs); // Signed lhs, unsigned rhs + V3Number& opPowSS (const V3Number& lhs, const V3Number& rhs); // Signed lhs, signed rhs + V3Number& opPowUS (const V3Number& lhs, const V3Number& rhs); // Unsigned lhs, signed rhs V3Number& opAnd (const V3Number& lhs, const V3Number& rhs); V3Number& opChangeXor(const V3Number& lhs, const V3Number& rhs); V3Number& opXor (const V3Number& lhs, const V3Number& rhs); diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 424220299..aeb484ca1 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -614,7 +614,7 @@ private: } } virtual void visit(AstPow* nodep, AstNUser* vup) { - // Pow is special, output sign only depends on LHS sign + // Pow is special, output sign only depends on LHS sign, but function result depends on both signs // Real if either side is real (as with AstAdd) shift_prelim(nodep, vup); if (nodep->lhsp()->isDouble() || nodep->rhsp()->isDouble()) { @@ -622,21 +622,46 @@ private: spliceCvtD(nodep->rhsp()); replaceWithDVersion(nodep); nodep=NULL; } else { - AstNodeBiop* newp = shift_final(nodep, vup); nodep=NULL; - newp->dtypeChgSigned(newp->lhsp()->isSigned()); - if (newp->isSigned()) { - replaceWithUOrSVersion(newp, false); newp=NULL; + if (vup->c()->final()) { + int width=nodep->width(); int ewidth=nodep->widthMin(); + nodep->lhsp()->iterateAndNext(*this,WidthVP(width,ewidth,FINAL).p()); + // rhs already finalized in shift_prelim + widthCheck(nodep,"LHS",nodep->lhsp(),width,ewidth); + nodep->dtypeChgSigned(nodep->lhsp()->isSigned()); + AstNode* newp = NULL; // No change + if (nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned()) { + newp = new AstPowSS (nodep->fileline(), nodep->lhsp()->unlinkFrBack(), + nodep->rhsp()->unlinkFrBack()); + } else if (nodep->lhsp()->isSigned() && !nodep->rhsp()->isSigned()) { + newp = new AstPowSU (nodep->fileline(), nodep->lhsp()->unlinkFrBack(), + nodep->rhsp()->unlinkFrBack()); + } else if (!nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned()) { + newp = new AstPowUS (nodep->fileline(), nodep->lhsp()->unlinkFrBack(), + nodep->rhsp()->unlinkFrBack()); + } + if (newp) { + newp->dtypeFrom(nodep); + UINFO(9,"powOld "<replaceWith(newp); nodep=NULL; + } } } } - virtual void visit(AstPowS* nodep, AstNUser* vup) { - // Pow is special, output sign only depends on LHS sign - shift_prelim(nodep, vup); - AstNodeBiop* newp = shift_final(nodep, vup); nodep=NULL; - newp->dtypeChgSigned(newp->lhsp()->isSigned()); - if (!newp->isSigned()) { - replaceWithUOrSVersion(newp, true); newp=NULL; - } + virtual void visit(AstPowSU* nodep, AstNUser* vup) { + // POWSU/SS/US only created here, dtype already determined, so nothing to do in this function + nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p()); + nodep->rhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p()); + } + virtual void visit(AstPowSS* nodep, AstNUser* vup) { + // POWSU/SS/US only created here, dtype already determined, so nothing to do in this function + nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p()); + nodep->rhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p()); + } + virtual void visit(AstPowUS* nodep, AstNUser* vup) { + // POWSU/SS/US only created here, dtype already determined, so nothing to do in this function + nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p()); + nodep->rhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p()); } virtual void visit(AstCountOnes* nodep, AstNUser* vup) { if (vup->c()->prelim()) { @@ -2533,8 +2558,6 @@ private: case AstType::atMODDIVS: newp = new AstModDiv (fl,lhsp,rhsp); break; case AstType::atMUL: newp = new AstMulS (fl,lhsp,rhsp); break; case AstType::atMULS: newp = new AstMul (fl,lhsp,rhsp); break; - case AstType::atPOW: newp = new AstPowS (fl,lhsp,rhsp); break; - case AstType::atPOWS: newp = new AstPow (fl,lhsp,rhsp); break; case AstType::atSHIFTR: newp = new AstShiftRS (fl,lhsp,rhsp); break; case AstType::atSHIFTRS: newp = new AstShiftR (fl,lhsp,rhsp); break; default: diff --git a/test_regress/t/t_math_pow.v b/test_regress/t/t_math_pow.v index 49839e13a..285d0b620 100644 --- a/test_regress/t/t_math_pow.v +++ b/test_regress/t/t_math_pow.v @@ -3,6 +3,12 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2005 by Wilson Snyder. +`ifdef VERILATOR + `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) +`else + `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) +`endif + module t (/*AUTOARG*/ // Inputs clk @@ -28,11 +34,13 @@ module t (/*AUTOARG*/ $write("%0x %x %x\n", cyc, p, shifted); `endif // Constant versions - if (61'h1 ** 21'h31 != 61'h1) $stop; - if (61'h2 ** 21'h10 != 61'h10000) $stop; - if (61'd10 ** 21'h3 != 61'h3e8) $stop; - if (61'h3 ** 21'h7 != 61'h88b) $stop; - if (61'h7ab3811219 ** 21'ha6e30 != 61'h01ea58c703687e81) $stop; + `checkh(61'h1 ** 21'h31, 61'h1); + `checkh(61'h2 ** 21'h10, 61'h10000); + `checkh(61'd10 ** 21'h3, 61'h3e8); + `checkh(61'h3 ** 21'h7, 61'h88b); +`ifndef VCS + `checkh(61'h7ab3811219 ** 21'ha6e30, 61'h01ea58c703687e81); +`endif if (cyc==1) begin a <= 61'h0; b <= 21'h0; @@ -71,25 +79,25 @@ module t (/*AUTOARG*/ 32'd01: ; 32'd02: ; // 0^x is indeterminate 32'd03: ; // 0^x is indeterminate - 32'd04: if (p!=61'h1) $stop; - 32'd05: if (p!=61'h10000) $stop; - 32'd06: if (p!=61'h3e8) $stop; - 32'd07: if (p!=61'h88b) $stop; - 32'd08: if (p!=61'h01ea58c703687e81) $stop; - 32'd09: if (p!=61'h01ea58c703687e81) $stop; + 32'd04: `checkh(p, 61'h1); + 32'd05: `checkh(p, 61'h10000); + 32'd06: `checkh(p, 61'h3e8); + 32'd07: `checkh(p, 61'h88b); + 32'd08: `checkh(p, 61'h01ea58c703687e81); + 32'd09: `checkh(p, 61'h01ea58c703687e81); default: $stop; endcase case (cyc) 32'd00: ; 32'd01: ; - 32'd02: if (shifted!=61'h0000000000000001) $stop; - 32'd03: if (shifted!=61'h0000000000000008) $stop; - 32'd04: if (shifted!=61'h0002000000000000) $stop; - 32'd05: if (shifted!=61'h0000000000010000) $stop; - 32'd06: if (shifted!=61'h0000000000000008) $stop; - 32'd07: if (shifted!=61'h0000000000000080) $stop; - 32'd08: if (shifted!=61'h0000000000000000) $stop; - 32'd09: if (shifted!=61'h0000000000000000) $stop; + 32'd02: `checkh(shifted, 61'h0000000000000001); + 32'd03: `checkh(shifted, 61'h0000000000000008); + 32'd04: `checkh(shifted, 61'h0002000000000000); + 32'd05: `checkh(shifted, 61'h0000000000010000); + 32'd06: `checkh(shifted, 61'h0000000000000008); + 32'd07: `checkh(shifted, 61'h0000000000000080); + 32'd08: `checkh(shifted, 61'h0000000000000000); + 32'd09: `checkh(shifted, 61'h0000000000000000); default: $stop; endcase end diff --git a/test_regress/t/t_math_pow2.pl b/test_regress/t/t_math_pow2.pl new file mode 100755 index 000000000..f91289753 --- /dev/null +++ b/test_regress/t/t_math_pow2.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_math_pow2.v b/test_regress/t/t_math_pow2.v new file mode 100644 index 000000000..e15c5b673 --- /dev/null +++ b/test_regress/t/t_math_pow2.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Aggregate outputs into a single result vector + //wire [31:0] pow32b = {24'h0,crc[15:8]}**crc[7:0]; // Overflows + wire [3:0] pow4b = crc[7:4]**crc[3:0]; + wire [63:0] result = {60'h0, pow4b}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h1fec4b2b71cf8024 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_math_pow3.pl b/test_regress/t/t_math_pow3.pl new file mode 100755 index 000000000..5ebc6a457 --- /dev/null +++ b/test_regress/t/t_math_pow3.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_math_pow3.v b/test_regress/t/t_math_pow3.v new file mode 100644 index 000000000..2ea68f740 --- /dev/null +++ b/test_regress/t/t_math_pow3.v @@ -0,0 +1,83 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +`ifdef VERILATOR + `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) +`else + `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) +`endif + +module t (/*AUTOARG*/); + + // IEEE says for ** the size is L(i). Thus Icarus Verilog is wrong in sizing some of the below. + + initial begin + // NC=67b6cfc1b29a21 VCS=c1b29a20(wrong) IV=67b6cfc1b29a21 Verilator=67b6cfc1b29a21 + $display("15 ** 14 = %0x expect 67b6cfc1b29a21", 64'b1111 ** 64'b1110); + // NC=1 VCS=0 IV=0 Verilator=1 (wrong,fixed) + $display("15 **-4'sd2 = %0x expect 0 (per IEEE negative power)", ((-4'd1 ** -4'sd2))); + // NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1 + $display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((-4'd1 ** -4'd2))); + // NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1 + $display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((4'd15 ** 4'd14))); + // NC=8765432187654321 VCS=8765432187654000(wrong) IV=8765432187654321 Verilator=8765432187654321 + $display("64'big ** 1 = %0x expect %0x", 64'h8765432187654321 ** 1, 64'h8765432187654321); + $display("\n"); + + `checkh( (64'b1111 ** 64'b1110), 64'h67b6cfc1b29a21); + `checkh( (-4'd1 ** -4'sd2), 4'h0); //bug730 + `checkh( (-4'd1 ** -4'd2), 4'h1); + `checkh( (4'd15 ** 4'd14), 4'h1); + `checkh( (64'h8765432187654321 ** 4'h1), 64'h8765432187654321); + + `checkh((-8'sh3 ** 8'h3) , 8'he5 ); // a**b (-27) + `checkh((-8'sh1 ** 8'h2) , 8'h1 ); // -1^odd=-1, -1^even=1 + `checkh((-8'sh1 ** 8'h3) , 8'hff ); // -1^odd=-1, -1^even=1 + `checkh(( 8'h0 ** 8'h3) , 8'h0 ); // 0 + `checkh(( 8'h1 ** 8'h3) , 8'h1 ); // 1 + `checkh(( 8'h3 ** 8'h3) , 8'h1b ); // a**b (27) + `checkh(( 8'sh3 ** 8'h3) , 8'h1b ); // a**b (27) + `checkh(( 8'h6 ** 8'h3) , 8'hd8 ); // a**b (216) + `checkh(( 8'sh6 ** 8'h3) , 8'hd8 ); // a**b (216) + + `checkh((-8'sh3 ** 8'sh3), 8'he5 ); // a**b + `checkh((-8'sh1 ** 8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 + `checkh((-8'sh1 ** 8'sh3), 8'hff ); // -1^odd=-1, -1^even=1 + `checkh(( 8'h0 ** 8'sh3), 8'h0 ); // 0 + `checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1 + `checkh(( 8'h3 ** 8'sh3), 8'h1b ); // a**b (27) + `checkh(( 8'sh3 ** 8'sh3), 8'h1b ); // a**b (27) + `checkh(( 8'h6 ** 8'sh3), 8'hd8 ); // a**b (216) + `checkh(( 8'sh6 ** 8'sh3), 8'hd8 ); // a**b (216) + + `checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 + + `checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 + + `checkh((-8'sh3 ** -8'sh3), 8'h0 ); // 0 (a<-1) // NCVERILOG bug + `checkh((-8'sh1 ** -8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 + `checkh((-8'sh1 ** -8'sh3), 8'hff); // -1^odd=-1, -1^even=1 +// `checkh(( 8'h0 ** -8'sh3), 8'hx ); // x // NCVERILOG bug + `checkh(( 8'h1 ** -8'sh3), 8'h1 ); // 1**b always 1 + `checkh(( 8'h3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug + `checkh(( 8'sh3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug + + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_math_precedence.pl index 7058e622f..94fb7ebdc 100755 --- a/test_regress/t/t_math_precedence.pl +++ b/test_regress/t/t_math_precedence.pl @@ -7,6 +7,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +!$Self->{vcs} or $Self->unsupported("VCS does ** wrong"); + compile ( ); diff --git a/test_regress/t/t_math_precedence.v b/test_regress/t/t_math_precedence.v index 49bffcd41..b22042c31 100644 --- a/test_regress/t/t_math_precedence.v +++ b/test_regress/t/t_math_precedence.v @@ -48,11 +48,7 @@ module t (/*AUTOARG*/ // Do a few in each group wire [1:0] o1 = ~ a; // Can't get more than one reduction to parse wire [1:0] o2 = ^ b; // Can't get more than one reduction to parse -`ifdef verilator - wire [1:0] o3 = a ** b ** c; -`else // A commercial simulator gets this wrong, so calc manually - wire [1:0] o3 = pow(pow(a,b),c); -`endif + wire [1:0] o3 = a ** b ** c; // Some simulators botch this wire [1:0] o4 = a * b / cnz % dnz * enz; wire [1:0] o5 = a + b - c + d; @@ -68,13 +64,8 @@ module t (/*AUTOARG*/ wire [1:0] o15 = a ? b : c ? d : e; // Now cross each pair of groups -`ifdef verilator - wire [1:0] x1 = ~ a ** ~ b ** ~c; - wire [1:0] x2 = a ** b * c ** d; -`else - wire [1:0] x1 = pow(pow(~ a, ~ b), ~c); - wire [1:0] x2 = pow(a,b) * pow(c,d); -`endif + wire [1:0] x1 = ~ a ** ~ b ** ~c; // Some simulators botch this + wire [1:0] x2 = a ** b * c ** d; // Some simulators botch this wire [1:0] x3 = a + b * c + d; wire [1:0] x4 = a + b << c + d; wire [1:0] x5 = a == b << c == d; @@ -160,7 +151,7 @@ module t (/*AUTOARG*/ $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h34b4e0b25bb03880 +`define EXPECTED_SUM 64'h2756ea365ec7520e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish;