luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Support SV 2012 package import before port list.

This commit is contained in:
Wilson Snyder 2014-05-15 20:50:42 -04:00
parent d7e4bc1379
commit f62bc6a2e5
3 changed files with 17 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Changes
View File

@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.861 devel * Verilator 3.861 devel
*** Support SV 2012 package import before port list.
**** Fix huge shifts to zero with -Wno-WIDTH, bug765. [Clifford Wolf] **** Fix huge shifts to zero with -Wno-WIDTH, bug765. [Clifford Wolf]

13
src/verilog.y
View File

@ -727,6 +727,11 @@ package_or_generate_item_declaration<nodep>: // ==IEEE: package_or_generate_item
| ';' { $$ = NULL; } | ';' { $$ = NULL; }
; ;
package_import_declarationList<nodep>:
package_import_declaration { $$ = $1; }
| package_import_declarationList package_import_declaration { $$ = $1->addNextNull($2); }
;
package_import_declaration<nodep>: // ==IEEE: package_import_declaration package_import_declaration<nodep>: // ==IEEE: package_import_declaration
yIMPORT package_import_itemList ';' { $$ = $2; } yIMPORT package_import_itemList ';' { $$ = $2; }
; ;
@ -753,7 +758,7 @@ package_import_itemObj<strp>: // IEEE: part of package_import_item
module_declaration: // ==IEEE: module_declaration module_declaration: // ==IEEE: module_declaration
// // timeunits_declaration instead in module_item // // timeunits_declaration instead in module_item
// // IEEE: module_nonansi_header + module_ansi_header // // IEEE: module_nonansi_header + module_ansi_header
modFront parameter_port_listE portsStarE ';' modFront importsAndParametersE portsStarE ';'
module_itemListE yENDMODULE endLabelE module_itemListE yENDMODULE endLabelE
{ $1->modTrace(v3Global.opt.trace() && $1->fileline()->tracingOn()); // Stash for implicit wires, etc { $1->modTrace(v3Global.opt.trace() && $1->fileline()->tracingOn()); // Stash for implicit wires, etc
if ($2) $1->addStmtp($2); if ($3) $1->addStmtp($3); if ($2) $1->addStmtp($2); if ($3) $1->addStmtp($3);
@ -783,6 +788,12 @@ modFront<modulep>:
SYMP->pushNew($$); } SYMP->pushNew($$); }
; ;
importsAndParametersE<nodep>: // IEEE: common part of module_declaration, interface_declaration, program_declaration
// // { package_import_declaration } [ parameter_port_list ]
parameter_port_listE { $$ = $1; }
| package_import_declarationList parameter_port_listE { $$ = $1->addNextNull($2); }
;
udpFront<modulep>: udpFront<modulep>:
yPRIMITIVE lifetimeE idAny yPRIMITIVE lifetimeE idAny
{ $$ = new AstPrimitive($1,*$3); $$->inLibrary(true); { $$ = new AstPrimitive($1,*$3); $$->inLibrary(true);

6
test_regress/t/t_package_twodeep.v
View File

@ -14,14 +14,14 @@ package pkg1;
parameter PARAM1 = 8; parameter PARAM1 = 8;
endpackage // pkg1 endpackage // pkg1
module t (/*AUTOARG*/ module t
import pkg1::*; // Test SV 2012 import format
(/*AUTOARG*/
// Inputs // Inputs
clk clk
); );
input clk; input clk;
import pkg1::*;
reg [PARAM1:0] bus1; reg [PARAM1:0] bus1;
initial begin initial begin